DS90UB914Q-Q1 Series

10-MHz to 100-MHz 10/12-bit FPD-Link III deserializer

Catalog

10-MHz to 100-MHz 10/12-bit FPD-Link III deserializer

Part	Supplier Device Package	Number of Outputs	Function	Output Type	Number of Inputs	Qualification	Input Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Grade	Mounting Type	Data Rate	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments DS90UB914QSQE/NOPB	48-WQFN (7x7)	12	Deserializer	LVCMOS	1	AEC-Q100	FPD-Link III LVDS	1.89 V 3.6 V	1.71 V 3 V	48-WFQFN Exposed Pad	Automotive	Surface Mount	1.4 Gbps	105 °C	-40 °C
Texas Instruments DS90UB914QSQX/NOPB	48-WQFN (7x7)	12	Deserializer	LVCMOS	1	AEC-Q100	FPD-Link III LVDS	1.89 V 3.6 V	1.71 V 3 V	48-WFQFN Exposed Pad	Automotive	Surface Mount	1.4 Gbps	105 °C	-40 °C
Texas Instruments DS90UB914ATRHSRQ1	48-WQFN (7x7)	12	Deserializer	LVCMOS	1	AEC-Q100	FPD-Link III LVDS	3.6 V	1.71 V	48-WFQFN Exposed Pad	Automotive	Surface Mount	1.4 Gbps	105 °C	-40 °C
Texas Instruments DS90UB914QSQ/NOPB	48-WQFN (7x7)	12	Deserializer	LVCMOS	1	AEC-Q100	FPD-Link III LVDS	1.89 V 3.6 V	1.71 V 3 V	48-WFQFN Exposed Pad	Automotive	Surface Mount	1.4 Gbps	105 °C	-40 °C

Catalog

10-MHz to 100-MHz 10/12-bit FPD-Link III deserializer

Key Features

• 10-MHz to 100-MHz Input Pixel Clock SupportSingle Differential Pair InterconnectProgrammable Data Payload:10-bit Payload up to 100 MHz12-bit Payload up to 75 MHzContinuous Low Latency Bidirectional ControlInterface Channel With I2C Support at 400 kHz2:1 Multiplexer to Choose Between Two InputImagersEmbedded Clock With DC-Balanced Coding toSupport AC-Coupled InterconnectsCapable of Driving up to 25 Meters ShieldedTwisted-PairReceive Equalizer Automatically Adapts forChanges in Cable LossFour Dedicated General-Purpose Input/OutputPins (GPIO) Available on Both Serializer andDeserializerLOCK Output Reporting Pin and AT-SPEED BISTDiagnosis Feature to Validate Link Integrity1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputson SerializerSingle Power Supply at 1.8 VISO 10605 and IEC 61000-4-2 ESD CompliantAutomotive-Grade Product: AEC-Q100 Grade 2QualifiedTemperature Range −40°C to +105°CSmall Serializer Footprint (5 mm × 5 mm)EMI/EMC Mitigation on DeserializerProgrammable Spread Spectrum (SSCG)OutputsReceiver Staggered Outputs10-MHz to 100-MHz Input Pixel Clock SupportSingle Differential Pair InterconnectProgrammable Data Payload:10-bit Payload up to 100 MHz12-bit Payload up to 75 MHzContinuous Low Latency Bidirectional ControlInterface Channel With I2C Support at 400 kHz2:1 Multiplexer to Choose Between Two InputImagersEmbedded Clock With DC-Balanced Coding toSupport AC-Coupled InterconnectsCapable of Driving up to 25 Meters ShieldedTwisted-PairReceive Equalizer Automatically Adapts forChanges in Cable LossFour Dedicated General-Purpose Input/OutputPins (GPIO) Available on Both Serializer andDeserializerLOCK Output Reporting Pin and AT-SPEED BISTDiagnosis Feature to Validate Link Integrity1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputson SerializerSingle Power Supply at 1.8 VISO 10605 and IEC 61000-4-2 ESD CompliantAutomotive-Grade Product: AEC-Q100 Grade 2QualifiedTemperature Range −40°C to +105°CSmall Serializer Footprint (5 mm × 5 mm)EMI/EMC Mitigation on DeserializerProgrammable Spread Spectrum (SSCG)OutputsReceiver Staggered Outputs

Description

The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package. The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package.