Texas Instruments

The TPS65232 provides one PWM buck controller, two adjustable, synchronous buck regulators. The SMPS have integrated switching FETs for optimized power efficiency and reduced external component count. All power blocks have thermal and over current/short circuit protection. The TPS65232 startup timing can be controlled through buck enable pins. The buck controller and buck converters have internal pole/zero pairs to help stabilizing the system with minimum external components. The TPS65232 provides one PWM buck controller, two adjustable, synchronous buck regulators. The SMPS have integrated switching FETs for optimized power efficiency and reduced external component count. All power blocks have thermal and over current/short circuit protection. The TPS65232 startup timing can be controlled through buck enable pins. The buck controller and buck converters have internal pole/zero pairs to help stabilizing the system with minimum external components.

Designed for analog and digital satellite receivers, the TPS65233-1 is a monolithic voltage regulator with I2C interface, specifically to provide the 13-V/18-V power supply and the 22-kHz tone signaling to the LNB down-converter in the antenna dish or to the multi-switch box. It offers a complete solution with very low component count, low power dissipation together with simple design and I2C standard interfacing. TPS65233-1 features high power efficiency. The boost converter integrates a 120-mΩ power MOSFET running at 1-MHz switching frequency. Drop out voltage at the linear regulator is 0.8 V to minimize power loss. TPS65233-1 provides multiple ways to generate the 22-kHz signal. Integrated linear regulator with push-pull output stage generates clean 22-kHz tone signal superimposed at the output even at zero loading. Current limit of linear regulator can be programmed by external resistor with ±10% accuracy. Full range of diagnostic read by I2C is available for system monitoring. The part is available in a 16-pin WQFN 3.00-mm × 3.00-mm (RTE) package. Designed for analog and digital satellite receivers, the TPS65233-1 is a monolithic voltage regulator with I2C interface, specifically to provide the 13-V/18-V power supply and the 22-kHz tone signaling to the LNB down-converter in the antenna dish or to the multi-switch box. It offers a complete solution with very low component count, low power dissipation together with simple design and I2C standard interfacing. TPS65233-1 features high power efficiency. The boost converter integrates a 120-mΩ power MOSFET running at 1-MHz switching frequency. Drop out voltage at the linear regulator is 0.8 V to minimize power loss. TPS65233-1 provides multiple ways to generate the 22-kHz signal. Integrated linear regulator with push-pull output stage generates clean 22-kHz tone signal superimposed at the output even at zero loading. Current limit of linear regulator can be programmed by external resistor with ±10% accuracy. Full range of diagnostic read by I2C is available for system monitoring. The part is available in a 16-pin WQFN 3.00-mm × 3.00-mm (RTE) package.

Designed for analog and digital satellite receivers, the TPS65235-1 is a monolithic voltage regulator with I 2C interface; specifically to provide the 13-V to 18-V power supply and the 22-kHz tone signal to the LNB down converter in the antenna dish or to the multi-switch box. The device offers a complete solution with minimum component count, low power dissipation together with simple design and I 2C standard interface. The TPS65235-1 features high power efficiency. The boost converter integrates a 140-mΩ power MOSFET running at 1-MHz or 500-kHz selectable switching frequency. Drop out voltage at the linear regulator is 0.8 V to minimize power loss. The TPS65235-1 provides multiple ways to generate the 22-kHz signal. Integrated linear regulator with push-pull output stage generates 22-kHz tone signal superimposed at the output even at zero loading. Current limit of linear regulator can be programmed by external resistor with ±10% accuracy. Full range of diagnostic read by I 2C is available for system monitoring. The TPS65235-1 has a special design at FCCM mode to avoid the audible noise especially when VIN is higher or closer to the VLNB output. The TPS65235-1 supports advanced DiSEqC 2.x standard with 22-kHz tone detection circuit and output interface. Designed for analog and digital satellite receivers, the TPS65235-1 is a monolithic voltage regulator with I 2C interface; specifically to provide the 13-V to 18-V power supply and the 22-kHz tone signal to the LNB down converter in the antenna dish or to the multi-switch box. The device offers a complete solution with minimum component count, low power dissipation together with simple design and I 2C standard interface. The TPS65235-1 features high power efficiency. The boost converter integrates a 140-mΩ power MOSFET running at 1-MHz or 500-kHz selectable switching frequency. Drop out voltage at the linear regulator is 0.8 V to minimize power loss. The TPS65235-1 provides multiple ways to generate the 22-kHz signal. Integrated linear regulator with push-pull output stage generates 22-kHz tone signal superimposed at the output even at zero loading. Current limit of linear regulator can be programmed by external resistor with ±10% accuracy. Full range of diagnostic read by I 2C is available for system monitoring. The TPS65235-1 has a special design at FCCM mode to avoid the audible noise especially when VIN is higher or closer to the VLNB output. The TPS65235-1 supports advanced DiSEqC 2.x standard with 22-kHz tone detection circuit and output interface.

The TPS65250 features three synchronous wide input range high efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- and 15-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP pin allows optimizing transient versus dc accuracy response with a simple RC compensation. The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or can be synchronized to an external clock connected to SYNC pin if needed. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. Both Bucks 2 and Buck 3 run in-phase and 180° out of phase with Buck 1 to minimize input filter requirements. TPS65250 features a unique storage and release circuitry for dying gasp mode. The storage capacitor is separated from input capacitor during normal operation. The storage and release circuit will charge the storage capacitor with a controlled circuit to reduce the inrush current from the adaptor supply to a storage voltage of 20 V to accumulate as much energy as possible taking advantage of the 1/2 CV2feature. TPS65250 continuously monitors the input voltage. Once the input voltage drops below a release voltage of 10.5 V, the circuit tries to transfer charge from storage capacitor to the input capacitor keeping the input voltage closer to release value for as long as possible. The release voltage should be set lower than the processor dying gasp detect voltage. This feature greatly reduces the capacitance required to support the dying gasp operation. The storage and release circuitry is completely on chip except for the charge and storage capacitors. The control circuit makes sure that the current charging the storage capacitor is limited during power up and the storage capacitor is fully charged to its target value before the end of reset (PGOOD pin) flag to the processor is released. The circuit also features a flag signal issued to the host circuit to indicate that the ‘dump’ stage is in process (GASP pin). This signal can be used to initiate the dying gasp process and reduce the system complexity. During the release process Buck 3 must stay enabled, but Buck 1 and Buck 2 can be disabled to maximize the release time. TPS65250 features a supervisor circuit that monitors Buck 1 and Buck 3 output voltage and generates an internal power good (PG) signal. The PGOOD pin is asserted once sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high. TPS65250 also features a low power mode enabled by an external signal, which allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. TPS65250 is packaged in a small, thermally efficient QFN RHA40 package. The TPS65250 features three synchronous wide input range high efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- and 15-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP pin allows optimizing transient versus dc accuracy response with a simple RC compensation. The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or can be synchronized to an external clock connected to SYNC pin if needed. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. Both Bucks 2 and Buck 3 run in-phase and 180° out of phase with Buck 1 to minimize input filter requirements. TPS65250 features a unique storage and release circuitry for dying gasp mode. The storage capacitor is separated from input capacitor during normal operation. The storage and release circuit will charge the storage capacitor with a controlled circuit to reduce the inrush current from the adaptor supply to a storage voltage of 20 V to accumulate as much energy as possible taking advantage of the 1/2 CV2feature. TPS65250 continuously monitors the input voltage. Once the input voltage drops below a release voltage of 10.5 V, the circuit tries to transfer charge from storage capacitor to the input capacitor keeping the input voltage closer to release value for as long as possible. The release voltage should be set lower than the processor dying gasp detect voltage. This feature greatly reduces the capacitance required to support the dying gasp operation. The storage and release circuitry is completely on chip except for the charge and storage capacitors. The control circuit makes sure that the current charging the storage capacitor is limited during power up and the storage capacitor is fully charged to its target value before the end of reset (PGOOD pin) flag to the processor is released. The circuit also features a flag signal issued to the host circuit to indicate that the ‘dump’ stage is in process (GASP pin). This signal can be used to initiate the dying gasp process and reduce the system complexity. During the release process Buck 3 must stay enabled, but Buck 1 and Buck 2 can be disabled to maximize the release time. TPS65250 features a supervisor circuit that monitors Buck 1 and Buck 3 output voltage and generates an internal power good (PG) signal. The PGOOD pin is asserted once sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high. TPS65250 also features a low power mode enabled by an external signal, which allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. TPS65250 is packaged in a small, thermally efficient QFN RHA40 package.

The TPS65251-x features three synchronous wide-input range, high-efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and close to the input supply. Each converter features an enable pin that allows a delayed start-up for sequencing purposes, soft-start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables the designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The current mode control allows a simple RC compensation. The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or can be synchronized to an external clock connected to the SYNC pin if needed. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. 180° out-of-phase operation between Buck 1 and Buck 2, 3 (Buck 2 and 3 run in phase) minimizes the input filter requirements. TPS65251-x features a supervisor circuit that monitors each converter output. The PGOOD pin is asserted when sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high. All converters feature an automatic low-power pulse PFM skipping mode, which improves efficiency during light loads and standby operation, while ensuring a very-low output ripple, allowing for a value of less than 2% at low output voltages. The TPS65251-x features three synchronous wide-input range, high-efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and close to the input supply. Each converter features an enable pin that allows a delayed start-up for sequencing purposes, soft-start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables the designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The current mode control allows a simple RC compensation. The switching frequency of the converters can either be set with an external resistor connected to ROSC pin or can be synchronized to an external clock connected to the SYNC pin if needed. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. 180° out-of-phase operation between Buck 1 and Buck 2, 3 (Buck 2 and 3 run in phase) minimizes the input filter requirements. TPS65251-x features a supervisor circuit that monitors each converter output. The PGOOD pin is asserted when sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the PGOOD signal is active high. All converters feature an automatic low-power pulse PFM skipping mode, which improves efficiency during light loads and standby operation, while ensuring a very-low output ripple, allowing for a value of less than 2% at low output voltages.

The TPS65252 features two synchronous wide input range high efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9- or 12-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP pin allows optimizing transient versus dc accuracy response with a simple RC compensation. The switching frequency of the converters can be set with an external resistor connected to ROSC pin. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between them to minimize the input filter requirements. TPS65252 also features a low power mode enabled by an external signal, which allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. The USB switch provides up to 1-A of current as required by downstream USB devices. When the output load exceeds the current-limit threshold selected with an external resistor or a short is present, the PMU limits the output current to a safe level by switching into a constant-current mode and pulling the over current logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to allow continuous non-interrupted operation the buck converters. The TPS65252 features a supervisor circuit that monitors both converters and provides a PGOOD signal (End of Reset) with a 256-ms timer. TPS65252 is packaged in a small, thermally efficient 28-pin QFN package. The TPS65252 features two synchronous wide input range high efficiency buck converters. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9- or 12-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The COMP pin allows optimizing transient versus dc accuracy response with a simple RC compensation. The switching frequency of the converters can be set with an external resistor connected to ROSC pin. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between them to minimize the input filter requirements. TPS65252 also features a low power mode enabled by an external signal, which allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. The USB switch provides up to 1-A of current as required by downstream USB devices. When the output load exceeds the current-limit threshold selected with an external resistor or a short is present, the PMU limits the output current to a safe level by switching into a constant-current mode and pulling the over current logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to allow continuous non-interrupted operation the buck converters. The TPS65252 features a supervisor circuit that monitors both converters and provides a PGOOD signal (End of Reset) with a 256-ms timer. TPS65252 is packaged in a small, thermally efficient 28-pin QFN package.

The TPS65253 features two synchronous wide input range high efficiency buck converters. The converters are designed to simplify product application while giving designers the options to optimize their usage according to the target application. The converters can operate in 5-, 9- and 12-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each converter features an enable pin that allows a delayed start-up for sequencing purposes, soft-start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The CMP pin allows optimizing transient versus dc accuracy response with a simple RC compensation. The switching frequency of the converters is set by an external resistor connected to ROSCpin. The switching regulators are designed to operate from 300 kHz to 1.2 MHz. The converters operate with 180° phase between then to minimize the input filter requirements. TPS65253 also features a low power mode enabled by an external signal, which allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. TPS65253 features a supervisor circuit that monitors both converters and provides a PGOOD signal (End of Reset) with a 32-ms timer. TPS65253 is packaged in a small, thermally efficient 28-pin QFN package. The TPS65253 features two synchronous wide input range high efficiency buck converters. The converters are designed to simplify product application while giving designers the options to optimize their usage according to the target application. The converters can operate in 5-, 9- and 12-V systems and have integrated power transistors. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus 1 V. Each converter features an enable pin that allows a delayed start-up for sequencing purposes, soft-start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIMx) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. The CMP pin allows optimizing transient versus dc accuracy response with a simple RC compensation. The switching frequency of the converters is set by an external resistor connected to ROSCpin. The switching regulators are designed to operate from 300 kHz to 1.2 MHz. The converters operate with 180° phase between then to minimize the input filter requirements. TPS65253 also features a low power mode enabled by an external signal, which allows for a reduction on the input power supplied to the system when the host processor is in stand-by (low activity) mode. TPS65253 features a supervisor circuit that monitors both converters and provides a PGOOD signal (End of Reset) with a 32-ms timer. TPS65253 is packaged in a small, thermally efficient 28-pin QFN package.

TPS65257 is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters operate in &145;hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter will see another over-current event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode will occur. The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between then to minimize the input filter requirements. All converters have peak current mode control which simplifies external frequency compensation. The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic oscillations in peak current mode control. A traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the crossover frequency over 100 kHz. All converters feature an automatic low power pulse PFM skipping mode which improves efficiency during light loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at low output voltages. The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP lower threshold which is 107%, the high side MOSFET is allowed to turn on the next clock cycle. TPS65257 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is active high. The push button operation has been designed to allow for automatic system start when the input supply is applied or to provide an integrated ON/OFF system management without the need of additional external components. The behavior of the device will depend on the status of the INT pin (see start-up signals). The USB switch provides up to 1-A of current as required by downstream USB devices. When the output load exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by switching into a constant-current mode and pulling the over current logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on operating. The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C. TPS65257 is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters operate in &145;hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter will see another over-current event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode will occur. The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between then to minimize the input filter requirements. All converters have peak current mode control which simplifies external frequency compensation. The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic oscillations in peak current mode control. A traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the crossover frequency over 100 kHz. All converters feature an automatic low power pulse PFM skipping mode which improves efficiency during light loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at low output voltages. The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP lower threshold which is 107%, the high side MOSFET is allowed to turn on the next clock cycle. TPS65257 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is active high. The push button operation has been designed to allow for automatic system start when the input supply is applied or to provide an integrated ON/OFF system management without the need of additional external components. The behavior of the device will depend on the status of the INT pin (see start-up signals). The USB switch provides up to 1-A of current as required by downstream USB devices. When the output load exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by switching into a constant-current mode and pulling the over current logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on operating. The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C.

TPS65258 is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters operate in ‘hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter will see another over-current event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode will occur. The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between then to minimize the input filter requirements. All converters have peak current mode control which simplifies external frequency compensation. The device has a built-in slope compensation ramp to prevent sub harmonic oscillations in peak current mode control. A traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the crossover frequency over 100 kHz. All converters feature an automatic low power pulse PFM skipping mode which improves efficiency during light loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at low output voltages. The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP lower threshold which is 107%, the high side MOSFET is allowed to turn on the next clock cycle. TPS65258 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is active high. The 2 USB switches provide up to 1-A of current as required by downstream USB devices. When the output load exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by switching into a constant-current mode and pulling the over current logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on operating. The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C. TPS65258 is a power management IC with three step-down buck converters. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. The converters are designed to simplify its application while giving the designer the option to optimize their usage according to the target application. The converters can operate in 5-, 9-, 12- or 15-V systems. The output voltage can be set externally using a resistor divider to any value between 0.8 V and the input supply minus the resistive drops on the converter path. Each converter features enable pin that allows a delayed start-up for sequencing purposes, soft start pin that allows adjustable soft-start time by choosing the soft-start capacitor, and a current limit (RLIM) pin that enables designer to adjust current limit by selecting an external resistor and optimize the choice of inductor. All converters operate in ‘hiccup mode’: Once an over-current lasting more than 10 ms is sensed in any of the converters, they will shut down for 10 ms and then the start-up sequencing will be tried again. If the overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter will see another over-current event and shuts down again repeating the cycle (hiccup) until the failure is cleared. If an overload condition lasts for less than 10 ms, only the relevant converter affected will shut-down and re-start and no global hiccup mode will occur. The switching frequency of the converters is set by an external resistor connected to ROSC pin. The switching regulators are designed to operate from 300 kHz to 2.2 MHz. The converters operate with 180° phase between then to minimize the input filter requirements. All converters have peak current mode control which simplifies external frequency compensation. The device has a built-in slope compensation ramp to prevent sub harmonic oscillations in peak current mode control. A traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the crossover frequency over 100 kHz. All converters feature an automatic low power pulse PFM skipping mode which improves efficiency during light loads and standby operation, while guaranteeing a very low output ripple, allowing for a value of less than 2% at low output voltages. The device incorporates an overvoltage transient protection circuit to minimize voltage overshoot. The OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVTP threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the FB voltage drops lower than the OVP lower threshold which is 107%, the high side MOSFET is allowed to turn on the next clock cycle. TPS65258 features a supervisor circuit which monitors each buck’s output and the PGOOD pin is asserted once sequencing is done. The PGOOD pin is an open drain output. The PGOOD pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. The PGOOD is pulled up when all converter outputs are more than 90% of its nominal output voltage. The default reset time is 100 ms. The polarity of the PGOOD is active high. The 2 USB switches provide up to 1-A of current as required by downstream USB devices. When the output load exceeds the current-limit threshold or a short is present, the PMU limits the output current to a safe level by switching into a constant-current mode and pulling the over current logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal warning protection circuit shuts off the USB switch and allows the buck converters to carry on operating. The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C. The thermal shutdown forces the device to stop operating when the junction temperature exceeds thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The thermal shutdown hysteresis is 20°C.