SN74HCT377 Series

High Speed CMOS Logic Octal D-Type Flip-Flop with Data Enable

Catalog

High Speed CMOS Logic Octal D-Type Flip-Flop with Data Enable

Part	Supplier Device Package	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Elements	Current - Quiescent (Iq)	Trigger Type	Function	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case [y]	Package / Case [y]	Mounting Type	Input Capacitance	Output Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case
Texas Instruments CD74HCT377ME4	20-SOIC	8	125 °C	-55 °C	50 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	38 ns	20-SOIC	0.295 in	7.5 mm	Surface Mount	10 pF	Non-Inverted	4 mA	4 mA	D-Type
Texas Instruments SN74HCT377DW	20-SOIC	8			37 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	28 ns	20-SOIC	0.295 in	7.5 mm	Surface Mount	3 pF	Non-Inverted	4 mA	4 mA	D-Type	85 °C	-40 °C
Texas Instruments SN74HCT377N	20-PDIP	8			37 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	28 ns	20-DIP			Through Hole	3 pF	Non-Inverted	4 mA	4 mA	D-Type	85 °C	-40 °C	7.62 mm	0.3 in
Texas Instruments CD74HCT377EG4	20-PDIP	8	125 °C	-55 °C	50 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	38 ns	20-DIP			Through Hole	10 pF	Non-Inverted	4 mA	4 mA	D-Type			7.62 mm	0.3 in
Texas Instruments SN74HCT377DWR	20-SOIC	8			37 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	28 ns	20-SOIC	0.295 in	7.5 mm	Surface Mount	3 pF	Non-Inverted	4 mA	4 mA	D-Type	85 °C	-40 °C
Texas Instruments CD74HCT377M	20-SOIC	8	125 °C	-55 °C	50 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	38 ns	20-SOIC	0.295 in	7.5 mm	Surface Mount	10 pF	Non-Inverted	4 mA	4 mA	D-Type
Texas Instruments CD74HCT377E	20-PDIP	8	125 °C	-55 °C	50 MHz	4.5 V	5.5 V	1	8 ÁA	Positive Edge	Standard	38 ns	20-DIP			Through Hole	10 pF	Non-Inverted	4 mA	4 mA	D-Type			7.62 mm	0.3 in

Catalog

High Speed CMOS Logic Octal D-Type Flip-Flop with Data Enable

Key Features

• Buffered Common ClockBuffered InputsTypical Propagation Delay at CL= 15pF, VCC= 5V, TA= 25°C14 ns (HC Types)16 ns (HCT Types)Fanout (Over Temperature Range)Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30%of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHBuffered Common ClockBuffered InputsTypical Propagation Delay at CL= 15pF, VCC= 5V, TA= 25°C14 ns (HC Types)16 ns (HCT Types)Fanout (Over Temperature Range)Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . –55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30%of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH

Description

These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\. These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.