SN74HCT595-Q1 Series

Automotive 8-bit shift register with TLL-compatible CMOS inputs and 3-state output registers

Catalog

Automotive 8-bit shift register with TLL-compatible CMOS inputs and 3-state output registers

Part	Function	Voltage - Supply [Min]	Voltage - Supply [Max]	Qualification	Logic Type	Package / Case [x]	Package / Case	Package / Case [y]	Number of Elements	Grade	Output Type	Mounting Type	Supplier Device Package	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]
Texas Instruments SN74HCT595QPWRQ1	Serial to Parallel	4.5 V	5.5 V	AEC-Q100	Shift Register	0.173 in	16-TSSOP	4.4 mm	1	Automotive	Tri-State	Surface Mount	16-TSSOP	8	-40 °C	125 °C

Catalog

Automotive 8-bit shift register with TLL-compatible CMOS inputs and 3-state output registers

Key Features

• AEC-Q100 qualified for automotive applications:Device temperature grade 1:–40°C to +125°C, TADevice HBM ESD Classification Level 2Device CDM ESD Classifcation Level C6LSTTL input logic compatibleVIL(max)= 0.8 V, VIH(min)= 2 VCMOS input logic compatibleII≤ 1 µA at VOL, VOH4.5 V to 5.5 V operationSupports fanout up to 10 LSTTL loadsShift register has direct clearAEC-Q100 qualified for automotive applications:Device temperature grade 1:–40°C to +125°C, TADevice HBM ESD Classification Level 2Device CDM ESD Classifcation Level C6LSTTL input logic compatibleVIL(max)= 0.8 V, VIH(min)= 2 VCMOS input logic compatibleII≤ 1 µA at VOL, VOH4.5 V to 5.5 V operationSupports fanout up to 10 LSTTL loadsShift register has direct clear

Description

The SN74HCT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput. The SN74HCT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput.