Analog Devices

The AD9177 is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores supporting up to eight baseband channels. The device is well suited for applications requiring wideband DACs to process signals of wide instantaneous bandwidth. The device features an 8-lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data receiver (JRx) port, an on-chip clock multiplier, and digital signal processing (DSP) datapaths capable of processing complex signals for wide-band or multiband direct to RF applications, phase array radar systems, and electronic warfare applications. The DSP datapaths can be bypassed to allow a direct connection between the data receiver port and the DAC cores.For direct digital synthesis (DDS) applications, the AD9177 can be operated without a data receiver port to generate multiple sine wave tones of varying frequencies. The main numerically controlled oscillator (NCO) block inside each of the four course digital upconverters (DUCs) contains one 48-bit NCO and a bank of thirty one 32-bit NCOs, each with an independent phase accumulator. Similarly, the main NCO block inside each of the course and fine digital downconverters (DDCs) in the receive datapath contains a bank of sixteen 48-bit NCOs that can be looped into the transmit datapath for processing ahead of the course DUCs and DAC outputs. Combined with general-purpose input/output (GPIO) controls for frequency hopping, preconfigurable profile selection, and the ability to synchronize the NCOs to a common trigger using the SYSREF input port, this bank allows phase coherent fast frequency hopping (FFH) for applications where multiple devices are synchronized or where NCO frequencies are continuously adjusted during operation.APPLICATIONSWireless communications infrastructureMicrowave point-to-point, E-band, and 5G mm waveBroadband communications systemsDOCSIS 3.1 and 4.0 CMTSPhased array radar and electronic warfareElectronic test and measurement systems

The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9200 uses a multistage differential pipeline architecture at 20 MSPS data rates and guarantees no missing codes over the full operating temperature range.The input of the AD9200 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially.The sample-and-hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit (AD9200ARS, AD9200KST). The dynamic performance is excellent.The AD9200 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit to determine low or high overflow.The AD9200 can operate with supply range from 2.7 V to 5.5 V, ideally suiting it for low power operation in high speed portable applications.The AD9200 is specified over the industrial (­40°C to +85°C) and commercial (0°C to +70°C) temperature ranges.PRODUCT HIGHLIGHTSLow PowerThe AD9200 consumes 80 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW.Very Small PackageThe AD9200 is available in both a 28-lead SSOP and 48-lead LQFP packages.Pin Compatible with AD876The AD9200 is pin compatible with the AD876, allowing older designs to migrate to lower supply voltages.300 MHz On-Board Sample-and-HoldThe versatile SHA input can be configured for either single-ended or differential inputs.Out-of-Range IndicatorThe OTR output bit indicates when the input signal is beyond the AD9200’s input range.Built-In Clamp FunctionAllows dc restoration of video signals with AD9200ARS and AD9200KST.

The AD9203 is a monolithic low power, single supply, 10-bit, 40 MSPS analog-to-digital converter with an on-chip voltage reference. It uses a multistage differential pipeline architecture at 40 MSPS data rate and guarantees no missing codes over the full operating temperature range. Its input range may be adjusted between 1 V and 2 VP-P.The ADC has an on-board programmable reference. An external reference can also be chosen to suit the DC accuracy and temperature drift requirements of an application. An external resistor can be used to reduce power consumption when operating at lower sampling rates.A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary or two's complement output format. An out-of-range signal (OTR) indicates an over-flow condition that can be used with the most significant bit to determine over-flow or under-flow. The AD9203 can operate with a supply range from 2.7 V to 3.6 V, attractive for low power operation in high-speed portable applications.Fabricated on an advanced CMOS process, the AD9203 is available in a 28-pin thin shrink small outline package (28 TSSOP) specified over the industrial temperature range (−40°C to +85°C).

The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus.The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).PRODUCT HIGHLIGHTSThe AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes.The AD9204 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with theAD926816-bit ADC, theAD9251andAD925814-bit ADCs, and theAD923112-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.APPLICATIONSCommunicationsDiversity radio systemsMultimode digital receiversGSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMAI/Q demodulation systemsSmart antenna systemsBattery-powered instrumentsHandheld scope metersUltrasoundRadar/LIDARPET/SPECT imaging

The AD9207 is a dual, 12-bit, 6 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support applications capable of direct sampling wideband signals up to 8 GHz. An onchip, low phase noise, phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, which simplifies the printed circuit board (PCB) distribution of a high frequency clock signal. A clock output buffer is available to transmit the ADC sampling clock to other devices.The dual ADC cores have code error rates (CER) better than 2 × 10−15. Low latency fast detection and signal monitoring are available for automatic gain control (AGC) purposes. A flexible 192-tap programmable finite impulse response filter (PFIR) is available for digital filtering and/or equalization. Programmable integer and fractional delay blocks support compensation for analog delay mismatches.The digital signal processing (DSP) block consists of two coarse digital downconverters (DDCs) and four fine DDCs per ADC pair. Each ADC can operate with one or two main DDC stages in support of multiband applications. The four additional fine DDC stages are available to support up to four bands per ADC. The 48-bit numerically controlled oscillators (NCOs) associated with each DDC support fast frequency hopping (FFH) while maintaining synchronization with up to 16 unique frequency assignments selected via the general-purpose input and output (GPIOx) pins or the serial port interface (SPI).The AD9207 supports one or two JTx links that can be configured for either JESD204B or JESD204C subclass operation, which allows different datapath configurations for each ADC. Multidevice synchronization is supported through the SYSREF± input pins.See the Outline Dimensions section and the Ordering Guide section of the data sheet for more information.APPLICATIONSWireless communications infrastructureMicrowave point to point, E-band, and 5G mmWaveBroadband communications systems, satellite communicationsDOCSIS 3.1 and 4.0 CMTSElectronic warfareElectronic test and measurement systems

The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution.The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C).PRODUCT HIGHLIGHTSHigh Performance—Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input.Low Power—Consumes only 410 mW @ 300 MSPS.Ease of Use—LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design.Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation.Pin-Compatible Family—12-bit pin-compatible family offered as AD9230.APPLICATIONSWireless and wired broadband communicationsCable reverse pathCommunications test equipmentRadar and satellite subsystemsPower amplifier linearization

The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate of up to 65 MSPS, it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTSSmall Footprint. Eight ADCs are contained in a small package.Low Power of 100 mW per Channel at 65 MSPS.Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate (DDR) operation.User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.Pin-Compatible Family. This includes theAD9222(12-bit) andAD9252(14-bit).APPLICATIONSMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversTape drivesOptical networkingTest equipment

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of −20°C to +115°C.