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SOIC (D)
Integrated Circuits (ICs)

SN74AHCT126DR

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Texas Instruments

4-CH, 4.5-V TO 5.5-V BUFFERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

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SOIC (D)
Integrated Circuits (ICs)

SN74AHCT126DR

Active
Texas Instruments

4-CH, 4.5-V TO 5.5-V BUFFERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74AHCT126DR
Current - Output High, Low [custom]8 mA
Current - Output High, Low [custom]8 mA
Logic TypeBuffer, Non-Inverting
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements4
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case14-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.46
10$ 0.38
25$ 0.34
100$ 0.26
250$ 0.23
500$ 0.19
1000$ 0.14
Digi-Reel® 1$ 0.46
10$ 0.38
25$ 0.34
100$ 0.26
250$ 0.23
500$ 0.19
1000$ 0.14
Tape & Reel (TR) 2500$ 0.13
5000$ 0.12
12500$ 0.12
25000$ 0.11
62500$ 0.10
Texas InstrumentsLARGE T&R 1$ 0.35
100$ 0.24
250$ 0.18
1000$ 0.12

Description

General part information

SN74AHCT126-Q1 Series

The SN74AHCT126-Q1 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74AHCT126-Q1 device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When OE is high, the respective gate passes the data from the A input to its Y output.