DS90UR124-Q1 Series
5-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer - Automotive Grade
Manufacturer: Texas Instruments
Catalog
5-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer - Automotive Grade
Key Features
• Supports displays with 18-bit color depth5MHz to 43MHz Pixel clockAutomotive-grade product AEC-Q100 grade 2 qualified24:1 Interface compressionEmbedded clock with DC balancing supports AC-coupled data transmissionCapable to drive up to 10 meters shielded twisted-pair cableNo reference clock required (deserializer)Meets ISO 10605 ESD – greater than 8kV HBM ESD structureHot plug supportEMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs@Speed BIST (Built-In Self-Test) to validate LVDS transmission pathIndividual power-down controls for both transmitter and receiverPower supply range 3.3V ±10%48-pin TQFP package for transmitter and 64-pin TQFP package for receiverTemperature range: –40°C to 105°CBackward-compatible mode with DS90C241/DS90C124Supports displays with 18-bit color depth5MHz to 43MHz Pixel clockAutomotive-grade product AEC-Q100 grade 2 qualified24:1 Interface compressionEmbedded clock with DC balancing supports AC-coupled data transmissionCapable to drive up to 10 meters shielded twisted-pair cableNo reference clock required (deserializer)Meets ISO 10605 ESD – greater than 8kV HBM ESD structureHot plug supportEMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs@Speed BIST (Built-In Self-Test) to validate LVDS transmission pathIndividual power-down controls for both transmitter and receiverPower supply range 3.3V ±10%48-pin TQFP package for transmitter and 64-pin TQFP package for receiverTemperature range: –40°C to 105°CBackward-compatible mode with DS90C241/DS90C124
Description
AI
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
