DS90LV049Q-Q1 Series

High temperature 3-V LVDS dual line driver and receiver pair

Catalog

High temperature 3-V LVDS dual line driver and receiver pair

Part	Mounting Type	Type	Qualification	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case [x]	Package / Case	Package / Case [y]	Data Rate	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Protocol	Duplex	Number of Drivers/Receivers [custom]	Number of Drivers/Receivers [custom]	Grade
Texas Instruments DS90LV049QMTX/NOPB	Surface Mount	Transceiver	AEC-Q100	3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	125 °C	-40 °C	16-TSSOP	LVDS	Full	2	2	Automotive
Texas Instruments DS90LV049HMTX/NOPB	Surface Mount	Transceiver		3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	125 °C	-40 °C	16-TSSOP	LVDS	Full	2	2
Texas Instruments DS90LV049TMTX/NOPB	Surface Mount	Transceiver		3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	85 °C	-40 °C	16-TSSOP	LVDS	Full	2	2
Texas Instruments DS90LV049HMT/NOPB	Surface Mount	Transceiver		3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	125 °C	-40 °C	16-TSSOP	LVDS	Full	2	2
Texas Instruments DS90LV049HMTX	Surface Mount	Transceiver		3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	125 °C	-40 °C	16-TSSOP	LVDS	Full	2	2
Texas Instruments DS90LV049TMT/NOPB	Surface Mount	Transceiver		3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	85 °C	-40 °C	16-TSSOP	LVDS	Full	2	2
Texas Instruments DS90LV049TMT	Surface Mount	Transceiver		3.6 V	3 V	0.173 in	16-TSSOP	4.4 mm	400 Mbps	85 °C	-40 °C		LVDS	Full	2	2

Catalog

High temperature 3-V LVDS dual line driver and receiver pair

Key Features

• AECQ-100 Grade 1Up to 400 Mbps Switching RatesFlow-Through Pinout Simplifies PCB Layout50 ps Typical Driver Channel-to-Channel Skew50 ps Typical Receiver Channel-to-Channel Skew3.3 V Single Power Supply DesignTRI-STATE Output ControlInternal Fail-Safe Biasing of Receiver InputsLow Power Dissipation (70 mW at 3.3 V Static)High Impedance on LVDS Outputs on Power DownConforms to TIA/EIA-644-A LVDS StandardAvailable in Low Profile 16 Pin TSSOP PackageAll trademarks are the property of their respective owners.AECQ-100 Grade 1Up to 400 Mbps Switching RatesFlow-Through Pinout Simplifies PCB Layout50 ps Typical Driver Channel-to-Channel Skew50 ps Typical Receiver Channel-to-Channel Skew3.3 V Single Power Supply DesignTRI-STATE Output ControlInternal Fail-Safe Biasing of Receiver InputsLow Power Dissipation (70 mW at 3.3 V Static)High Impedance on LVDS Outputs on Power DownConforms to TIA/EIA-644-A LVDS StandardAvailable in Low Profile 16 Pin TSSOP PackageAll trademarks are the property of their respective owners.

Description

The DS90LV049H is a dual CMOS differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV049H TSSOP package allows for flow-through routing for easy PCB layout. The DS90LV049H drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3-V CMOS signals. The LVDS input buffers have internal fail-safe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049H supports a TRI-STATE function for a low idle power state when the device is not in use. The EN andENinputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates. The DS90LV049H is a dual CMOS differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV049H TSSOP package allows for flow-through routing for easy PCB layout. The DS90LV049H drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3-V CMOS signals. The LVDS input buffers have internal fail-safe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049H supports a TRI-STATE function for a low idle power state when the device is not in use. The EN andENinputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates.