Texas Instruments

The \x92FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity-error (ERROR\) output. These devices can be used in odd-parity systems. ERROR\ is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several \x92FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual \x92FCT480T device. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity-error (ERROR\) output. These devices can be used in odd-parity systems. ERROR\ is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several \x92FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual \x92FCT480T device. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT543T octal latched transceivers contain two sets of eight D-type latches with separate latch-enable (LEAB\, LEBA\) and output-enable (OEAB\, OEBA\) inputs for each set to permit independent control of input and output in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB\) input must be low in order to enter data from A or to take data from B, as indicated in the function table. With CEAB\ low, a low signal on the A-to-B latch-enable (LEAB\) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB\ signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ low, the 3-state B-output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEBA\, LEBA\, and OEBA\ inputs. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT543T octal latched transceivers contain two sets of eight D-type latches with separate latch-enable (LEAB\, LEBA\) and output-enable (OEAB\, OEBA\) inputs for each set to permit independent control of input and output in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB\) input must be low in order to enter data from A or to take data from B, as indicated in the function table. With CEAB\ low, a low signal on the A-to-B latch-enable (LEAB\) input makes the A-to-B latches transparent; a subsequent low-to-high transition of the LEAB\ signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ low, the 3-state B-output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEBA\, LEBA\, and OEBA\ inputs. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The \x92FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The \x92FCT841T devices\x92 high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT138T devices are 1-of-8 decoders. These devices accept three binary weighted inputs (A0, A1, A2) and, when enabled, provide eight mutually exclusive active-low outputs (O\0\x96O\7). The \x92FCT138T devices feature three enable inputs: two active low (E\1, E\2) and one active high (E3). All outputs are high unless E\1and E\2are low and E3is high. This multiple-enable function allows easy parallel expansion of the device to a 1-of-32 (five lines to 32 lines) decoder with just four \x92FCT138T devices and one inverter. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT138T devices are 1-of-8 decoders. These devices accept three binary weighted inputs (A0, A1, A2) and, when enabled, provide eight mutually exclusive active-low outputs (O\0\x96O\7). The \x92FCT138T devices feature three enable inputs: two active low (E\1, E\2) and one active high (E3). All outputs are high unless E\1and E\2are low and E3is high. This multiple-enable function allows easy parallel expansion of the device to a 1-of-32 (five lines to 32 lines) decoder with just four \x92FCT138T devices and one inverter. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT157T devices are quad two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The output-enable (E\) input is active low. When E\ is high, all of the outputs (Y) are forced low, regardless of all other input conditions. Moving data from two groups of registers to four common output buses is a common use of the \x92FCT157T devices. The state of S determines the particular register from which the data comes. It also can be used as a function generator. These devices are useful for implementing highly irregular logic by generating any 4 of the 16 different functions of 2 variables, with 1 variable common. The \x92FCT157T devices are logic implementations of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT157T devices are quad two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The output-enable (E\) input is active low. When E\ is high, all of the outputs (Y) are forced low, regardless of all other input conditions. Moving data from two groups of registers to four common output buses is a common use of the \x92FCT157T devices. The state of S determines the particular register from which the data comes. It also can be used as a function generator. These devices are useful for implementing highly irregular logic by generating any 4 of the 16 different functions of 2 variables, with 1 variable common. The \x92FCT157T devices are logic implementations of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

These 16-bit buffer/line drivers are used in memory driver, clock driver, or other bus interface applications, where high speed and low power are required. With flow-through pinout and small shrink packaging, board layout is simplified. The three-state controls are designed to allow 4-, 8-, or 16-bit operation. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16240T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162240T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162240T is ideal for driving transmission lines. These 16-bit buffer/line drivers are used in memory driver, clock driver, or other bus interface applications, where high speed and low power are required. With flow-through pinout and small shrink packaging, board layout is simplified. The three-state controls are designed to allow 4-, 8-, or 16-bit operation. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16240T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162240T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162240T is ideal for driving transmission lines.

These 16-bit buffers/line drivers are designed for use in memory driver, clock driver, or other bus interface applications, where high-speed and low power are required. With flow-through pinout and small shrink packaging board layout is simplified. The three-state controls are designed to allow 4-bit, 8-bit or combined 16-bit operation. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16244T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162244T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162244T is ideal for driving transmission lines. The CY74FCT162H244T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. These 16-bit buffers/line drivers are designed for use in memory driver, clock driver, or other bus interface applications, where high-speed and low power are required. With flow-through pinout and small shrink packaging board layout is simplified. The three-state controls are designed to allow 4-bit, 8-bit or combined 16-bit operation. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16244T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162244T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162244T is ideal for driving transmission lines. The CY74FCT162H244T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

These 16-bit transceivers are designed for use in bidirectional synchronous communication between two buses, where high speed and low power are required. With the exception of the CY74FCT16245T, these devices can be operated either as two independent octals or a single 16-bit transceiver. Direction of data flow is controlled by (DIR), the Output Enable (OE\) transfers data when LOW and isolates the buses when HIGH. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16245T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162245T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162245T is ideal for driving transmission lines. The CY74FCT162H245T is a 24-mA balanced output part that has bus hold on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. These 16-bit transceivers are designed for use in bidirectional synchronous communication between two buses, where high speed and low power are required. With the exception of the CY74FCT16245T, these devices can be operated either as two independent octals or a single 16-bit transceiver. Direction of data flow is controlled by (DIR), the Output Enable (OE\) transfers data when LOW and isolates the buses when HIGH. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16245T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162245T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162245T is ideal for driving transmission lines. The CY74FCT162H245T is a 24-mA balanced output part that has bus hold on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

CY74FCT16373T and CY74FCT162373T are 16-bit D-type latches designed for use in bus applications requiring high speed and low power. These devices can be used as two independent 8-bit latches or as a single 16-bit latch by connecting the Output Enable (OE\) and Latch (LE) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16373T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162373T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162373T is ideal for driving transmission lines. CY74FCT16373T and CY74FCT162373T are 16-bit D-type latches designed for use in bus applications requiring high speed and low power. These devices can be used as two independent 8-bit latches or as a single 16-bit latch by connecting the Output Enable (OE\) and Latch (LE) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16373T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162373T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162373T is ideal for driving transmission lines.

CY74FCT16374T and CY74FCT162374T are 16-bit D-type registers designed for use as buffered registers in high-speed, low power bus applications. These devices can be used as two independent 8-bit registers or as a single 16-bit register by connecting the output Enable (OE) and Clock (CLK) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16374T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162374T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162374T is ideal for driving transmission lines. CY74FCT16374T and CY74FCT162374T are 16-bit D-type registers designed for use as buffered registers in high-speed, low power bus applications. These devices can be used as two independent 8-bit registers or as a single 16-bit register by connecting the output Enable (OE) and Clock (CLK) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16374T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162374T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162374T is ideal for driving transmission lines.