Texas Instruments

CY74FCT16374T and CY74FCT162374T are 16-bit D-type registers designed for use as buffered registers in high-speed, low power bus applications. These devices can be used as two independent 8-bit registers or as a single 16-bit register by connecting the output Enable (OE) and Clock (CLK) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16374T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162374T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162374T is ideal for driving transmission lines. CY74FCT16374T and CY74FCT162374T are 16-bit D-type registers designed for use as buffered registers in high-speed, low power bus applications. These devices can be used as two independent 8-bit registers or as a single 16-bit register by connecting the output Enable (OE) and Clock (CLK) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16374T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162374T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162374T is ideal for driving transmission lines.

The \x92FCT163T devices are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers. These devices have two types of count-enable (CEP and CET) inputs, plus a terminal-count (TC) output for versatility in forming synchronous multistaged counters. The \x92FCT163T devices have a synchronous-reset (SR\) input that overrides counting and parallel loading, and allows the outputs to be reset simultaneously on the rising edge of the clock. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT163T devices are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers. These devices have two types of count-enable (CEP and CET) inputs, plus a terminal-count (TC) output for versatility in forming synchronous multistaged counters. The \x92FCT163T devices have a synchronous-reset (SR\) input that overrides counting and parallel loading, and allows the outputs to be reset simultaneously on the rising edge of the clock. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT16543T and CY74FCT162543T are 16-bit, high-speed, low power latched transceivers that are organized as two independent 8-bit D-type latched transceivers containing two sets of eight D-type latches with separate Latch Enable (LEAB\, LEAB\) and Output Enable (OEAB\, OEAB\) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B input Enable (CEAB\) must be LOW in order to enter data from A or to take data from B as indicated in the truth table. With CAEB\ LOW, a LOW signal on the A-to-B Latch Enable (LEAB\) makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB\ signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ both LOW, the three-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB\, LEAB\, and OEAB\ inputs flow-through pinout and small shrink packaging and in simplifying board design. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162543T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162543T is ideal for driving transmission lines. The CY74FCT162H543T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. The CY74FCT16543T and CY74FCT162543T are 16-bit, high-speed, low power latched transceivers that are organized as two independent 8-bit D-type latched transceivers containing two sets of eight D-type latches with separate Latch Enable (LEAB\, LEAB\) and Output Enable (OEAB\, OEAB\) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B input Enable (CEAB\) must be LOW in order to enter data from A or to take data from B as indicated in the truth table. With CAEB\ LOW, a LOW signal on the A-to-B Latch Enable (LEAB\) makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB\ signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB\ and OEAB\ both LOW, the three-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB\, LEAB\, and OEAB\ inputs flow-through pinout and small shrink packaging and in simplifying board design. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162543T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162543T is ideal for driving transmission lines. The CY74FCT162H543T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA\ control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines. These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA\ control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines.

The CY74FCT16827T 20-bit buffer/line driver and the CY74FCT162827T 20-bit buffer/line driver provide high-performance bus interface buffering for wide data/address paths or buses carrying parity. These parts can be used as a single 20-bit buffer or two 10-bit buffers. Each 10-bit buffer has a pair of NANDed OE\ for increased flexibility. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16827T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162827T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162827T is ideal for driving transmission lines. The CY74FCT16827T 20-bit buffer/line driver and the CY74FCT162827T 20-bit buffer/line driver provide high-performance bus interface buffering for wide data/address paths or buses carrying parity. These parts can be used as a single 20-bit buffer or two 10-bit buffers. Each 10-bit buffer has a pair of NANDed OE\ for increased flexibility. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16827T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162827T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162827T is ideal for driving transmission lines.

The CY74FCT16841T and CY74FCT162841T are 20-bit D-type latches designed for use in bus applications requiring high speed and low power. These devices can be used as two independent 10-bit latches, or as a single 10-bit latch, or as a single 20-bit latch by connecting the Output Enable (OE\) and Latch (LE) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16841T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162841T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162841T is ideal for driving transmission lines. The CY74FCT16841T and CY74FCT162841T are 20-bit D-type latches designed for use in bus applications requiring high speed and low power. These devices can be used as two independent 10-bit latches, or as a single 10-bit latch, or as a single 20-bit latch by connecting the Output Enable (OE\) and Latch (LE) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16841T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162841T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162841T is ideal for driving transmission lines.

These 16-bit registered transceivers are high-speed, low-power devices. 16-bit operation is achieved by connecting the control lines of the two 8-bit registered transceivers together. For data flow from bus A-to-B, CEAB\ must be LOW to allow data to be stored when CLKAB transitions from LOW-to-HIGH. The stored data will be present on the output when OEAB\ is LOW. Control of data from B-to-A is similar and is controlled by using the CEBA\, CLKBA, and OEBA\ inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16952T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162952T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162952T is ideal for driving transmission lines. The CY74FCT162H952T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. These 16-bit registered transceivers are high-speed, low-power devices. 16-bit operation is achieved by connecting the control lines of the two 8-bit registered transceivers together. For data flow from bus A-to-B, CEAB\ must be LOW to allow data to be stored when CLKAB transitions from LOW-to-HIGH. The stored data will be present on the output when OEAB\ is LOW. Control of data from B-to-A is similar and is controlled by using the CEBA\, CLKBA, and OEBA\ inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16952T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162952T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162952T is ideal for driving transmission lines. The CY74FCT162H952T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input\x92s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs.

The CY74FCT191T is a reversible modulo-16 binary counter, featuring synchronous counting and asynchronous presetting. The preset allows the CY74FCT191T to be used in programmable dividers. The count enable input, terminal count output, and ripple-clock output make possible a variety of methods of implementing multiusage counters. In the counting modes, state changes are initiated by the rising edge of the clock. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT191T is a reversible modulo-16 binary counter, featuring synchronous counting and asynchronous presetting. The preset allows the CY74FCT191T to be used in programmable dividers. The count enable input, terminal count output, and ripple-clock output make possible a variety of methods of implementing multiusage counters. In the counting modes, state changes are initiated by the rising edge of the clock. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT2240T is an octal buffer and line driver that includes on-chip 25-terminating resistors at each of the outputs to minimize noise resulting from reflections or standing waves in high-performance applications. The on-chip resistors reduce overall board space and component count. Designed to be employed as a memory address driver, clock driver, and bus-oriented transmitter/receiver, this device provides speed and drive capabilities commensurate with its fastest bipolar logic counterparts, while reducing power dissipation. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices, without the need for external components. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT2240T is an octal buffer and line driver that includes on-chip 25-terminating resistors at each of the outputs to minimize noise resulting from reflections or standing waves in high-performance applications. The on-chip resistors reduce overall board space and component count. Designed to be employed as a memory address driver, clock driver, and bus-oriented transmitter/receiver, this device provides speed and drive capabilities commensurate with its fastest bipolar logic counterparts, while reducing power dissipation. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices, without the need for external components. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT2244T is an octal buffer and line driver that includes on-chip 25-terminating resistors at each of the outputs to minimize noise resulting from reflections or standing waves in high-performance applications. The on-chip resistors reduce overall board space and component count. Designed to be employed as a memory address driver, clock driver, and bus-oriented transmitter/receiver, this device provides speed and drive capabilities commensurate with its fastest bipolar logic counterparts, while reducing power dissipation. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices, without the need for external components. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT2244T is an octal buffer and line driver that includes on-chip 25-terminating resistors at each of the outputs to minimize noise resulting from reflections or standing waves in high-performance applications. The on-chip resistors reduce overall board space and component count. Designed to be employed as a memory address driver, clock driver, and bus-oriented transmitter/receiver, this device provides speed and drive capabilities commensurate with its fastest bipolar logic counterparts, while reducing power dissipation. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices, without the need for external components. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.