CY54FCT480T Series

Dual 8-Bit Parity Generator/Checker

Catalog

Dual 8-Bit Parity Generator/Checker

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]	Number of Circuits [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Logic Type	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case
Texas Instruments CY54FCT480BTLMB	4.75 V	5.25 V	11.43	28-LCCC	11.43	8	12 mA	32 mA	Surface Mount	Parity Generator/Checker	-55 °C	125 °C	28-CLCC

Catalog

Dual 8-Bit Parity Generator/Checker

Key Features

• Function, Pinout, and Drive Compatible With FCT and F LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsTwo 8-Bit Parity Generators/CheckersOpen-Drain Active-Low Parity-Error OutputExpandable for Larger Word WidthsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)CY54FCT480T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT480T64-mA Output Sink Current32-mA Output Source CurrentFunction, Pinout, and Drive Compatible With FCT and F LogicReduced VOH(Typically = 3.3 V) Versions of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsTwo 8-Bit Parity Generators/CheckersOpen-Drain Active-Low Parity-Error OutputExpandable for Larger Word WidthsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)CY54FCT480T32-mA Output Sink Current12-mA Output Source CurrentCY74FCT480T64-mA Output Sink Current32-mA Output Source Current

Description

The \x92FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity-error (ERROR\) output. These devices can be used in odd-parity systems. ERROR\ is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several \x92FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual \x92FCT480T device. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The \x92FCT480T devices are high-speed, dual, 8-bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parity-error (ERROR\) output. These devices can be used in odd-parity systems. ERROR\ is an open-drain output designed for easy expansion of the word width by a wired-OR connection of several \x92FCT480T devices. Because no additional logic is needed, the parity-generation or parity-checking times remain the same as for an individual \x92FCT480T device. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.