CDCLVP2106Low jitter, dual 1:6 universal-to-LVPECL buffer | Development Boards, Kits, Programmers | 2 | Active | The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package.
The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2106 clock buffer distributes two clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a 6-mm × 6-mm, VQFN-40 package. |
CDCLVP2108Low jitter, dual 1:8 universal-to-LVPECL buffer | Evaluation and Demonstration Boards and Kits | 3 | Active | The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a 7-mm × 7-mm, VQFN-48 package.
The CDCLVP2108 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2108 clock buffer distributes two clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2108 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2108 is characterized for operation from –40°C to +85°C and is available in a 7-mm × 7-mm, VQFN-48 package. |
CDCLVP215Dual 1:5 high speed LVPECL fan out buffer | Clock/Timing | 1 | Active | The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50-transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50.
The VBBreference voltage output is used if single-ended input operation is required. In this case, the VBBpin should be connected toCLKAorCLKBand bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP215 is characterized for operation from –40°C to 85°C.
The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50-transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50.
The VBBreference voltage output is used if single-ended input operation is required. In this case, the VBBpin should be connected toCLKAorCLKBand bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP215 is characterized for operation from –40°C to 85°C. |
CDCM1802Clock buffer with programmable divider, LVPECL I/O and LVCMOS output | Clock Buffers, Drivers | 1 | Active | The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 andY0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.
The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.
For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.
The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 andY0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.
The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C.
For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference. |
| Clock/Timing | 3 | Active | |
| Evaluation Boards | 1 | Active | |
CDCM610011:1 ultra-low jitter crystal-in clock generator | Clock/Timing | 3 | Active | The CDCM61001 is a highly versatile, low-jitter frequency synthesizer that can generate low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM61001 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61001 is available in a small, 32-pin, 5-mm × 5-mm QFN package.
The CDCM61001 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with one universal output buffer that can be configured to be LVPECL, LVDS, or LVCMOS compatible. The universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading in order to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output has an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and divider are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN. For a configuration setting for common wireline and datacom applications, refer to. For other applications, use to calculate the exact crystal oscillator frequency required for the desired output.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. shows a high-level block diagram of the CDCM61001.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C.
The CDCM61001 is a highly versatile, low-jitter frequency synthesizer that can generate low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM61001 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61001 is available in a small, 32-pin, 5-mm × 5-mm QFN package.
The CDCM61001 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with one universal output buffer that can be configured to be LVPECL, LVDS, or LVCMOS compatible. The universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading in order to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output has an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and divider are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN. For a configuration setting for common wireline and datacom applications, refer to. For other applications, use to calculate the exact crystal oscillator frequency required for the desired output.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. shows a high-level block diagram of the CDCM61001.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C. |
CDCM610021:2 ultra-low jitter crystal-in clock generator | Integrated Circuits (ICs) | 2 | Active | The CDCM61002 is a highly versatile, low-jitter frequency synthesizer that can generate two low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM61002 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61002 is available in a small, 32-pin, 5-mm × 5-mm QFN package.
The CDCM61002 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with two universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading in order to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The outputs share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividered are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN. For a configuration setting for common wireline and datacom applications, refer to. For other applications, use to calculate the exact crystal oscillator frequency required for the desired output.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. shows a high-level block diagram of the CDCM61002.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C.
The CDCM61002 is a highly versatile, low-jitter frequency synthesizer that can generate two low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal or LVCMOS input for a variety of wireline and data communication applications. The CDCM61002 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61002 is available in a small, 32-pin, 5-mm × 5-mm QFN package.
The CDCM61002 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with two universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading in order to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The outputs share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividered are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN. For a configuration setting for common wireline and datacom applications, refer to. For other applications, use to calculate the exact crystal oscillator frequency required for the desired output.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins. shows a high-level block diagram of the CDCM61002.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C. |
CDCM610041:4 ultra-low jitter crystal-in clock generator | Integrated Circuits (ICs) | 1 | Active | The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package.
The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins.CDCM61004 Block Diagramshows a high-level diagram of the CDCM61004.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.
The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package.
The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the1.75 GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN.
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins.CDCM61004 Block Diagramshows a high-level diagram of the CDCM61004.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C. |
CDCM62082:8 ultra-low power, low jitter clock generator | Development Boards, Kits, Programmers | 4 | Active | The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, Small Cells, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208 also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208 can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.
The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, Small Cells, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208 also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208 can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins. |
