CDCS503-Q1Automotive clock buffer/clock multiplier with optional SSC | Integrated Circuits (ICs) | 3 | Active | The CDCS503-Q1 device is a spread spectrum capable, LVCMOS input clock buffer with selectable frequency multiplication.
It shares major functionality with the CDCS502 but uses a LVCMOS input stage instead of the crystal input stage of the CDCS502, and the CDCS503-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.
The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock frequency with a triangular modulation.
By this, the device can generate output frequencies between 8 MHz and 108 MHz with or without SSC.
A separate control pin can be used to enable or disable the output. The CDCS503-Q1 device operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C, and available in an 8-pin TSSOP package.
The CDCS503-Q1 device is a spread spectrum capable, LVCMOS input clock buffer with selectable frequency multiplication.
It shares major functionality with the CDCS502 but uses a LVCMOS input stage instead of the crystal input stage of the CDCS502, and the CDCS503-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.
The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock frequency with a triangular modulation.
By this, the device can generate output frequencies between 8 MHz and 108 MHz with or without SSC.
A separate control pin can be used to enable or disable the output. The CDCS503-Q1 device operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C, and available in an 8-pin TSSOP package. |
| Clock Buffers, Drivers | 1 | Active | The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.
The CDCS504-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.
By this, the device can generate output frequencies between 2 MHz and 108 MHz.
A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.
The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication.
The CDCS504-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.
By this, the device can generate output frequencies between 2 MHz and 108 MHz.
A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package. |
CDCU2A8771.8-V phase-lock loop clock driver with high output drive for DDR2 SDRAM applications | Application Specific Clock/Timing | 3 | Active | The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to 10 differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDDis grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK,CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN,FBIN) and the clock input pair (CK,CK) within the specified stabilization time.
The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.
The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to 10 differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDDis grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK,CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN,FBIN) and the clock input pair (CK,CK) within the specified stabilization time.
The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C. |
CDCU877A1.8-V phase-lock loop clock driver for DDR2 SDRAM applications | Application Specific Clock/Timing | 18 | Active | The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to ten differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDDis grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK,CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN,FBIN) and the clock input pair (CK,CK) within the specified stabilization time.
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C.
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to ten differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDDis grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK,CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN,FBIN) and the clock input pair (CK,CK) within the specified stabilization time.
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C. |
| Application Specific Clock/Timing | 4 | Active | |
CDCUN1208LPUltra-low power, 2:8 fan-out buffer with universal inputs and outputs | Development Boards, Kits, Programmers | 2 | Active | The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry. |
CDCV304-EPenhanced product general purpose and PCI-X 1:4 clock buffer | Integrated Circuits (ICs) | 4 | Active | The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.
The CDCV304 is characterized for operation from –40°C to 105°C.
The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.
The CDCV304 is characterized for operation from –40°C to 105°C. |
| Clock/Timing | 3 | Obsolete | |
| Integrated Circuits (ICs) | 6 | NRND | The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.
When AVDDis tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges.
The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again and enables the outputs.
When AVDDis tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV855 is characterized for both commercial and industrial temperature ranges. |
CDCV857A2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications | Clock/Timing | 10 | NRND | The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.
When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.
The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.
When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C. |
