CDCM1802 Series

Clock buffer with programmable divider, LVPECL I/O and LVCMOS output

Catalog

Clock buffer with programmable divider, LVPECL I/O and LVCMOS output

Part	Type	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Voltage - Supply [Max]	Voltage - Supply [Min]	Ratio - Input:Output [custom]	Number of Circuits	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Output	Frequency - Max [Max]	Mounting Type	Supplier Device Package
Texas Instruments CDCM1802RGTR	Divider Fanout Buffer (Distribution) Multiplexer			3.6 V	3 V	1:2	1	85 °C	-40 °C	16-VFQFN Exposed Pad	LVCMOS LVPECL	800 MHz	Surface Mount	16-VQFN (3x3)

Catalog

Clock buffer with programmable divider, LVPECL I/O and LVCMOS output

Key Features

• Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended OutputProgrammable Output Divider for Both LVPECL and LVCMOS Outputs1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise3.3-V Power Supply (2.5-V Functional)Signaling Rate Up to 800-MHz LVPECL and200-MHz LVCMOSDifferential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input SignalsReceiver Input Threshold ±75 mV16-Pin VQFN Package (3.00 mm × 3.00 mm)Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended OutputProgrammable Output Divider for Both LVPECL and LVCMOS Outputs1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise3.3-V Power Supply (2.5-V Functional)Signaling Rate Up to 800-MHz LVPECL and200-MHz LVCMOSDifferential Input Stage for Wide Common-Mode Range Also Provides VBB Bias Voltage Output for Single-Ended Input SignalsReceiver Input Threshold ±75 mV16-Pin VQFN Package (3.00 mm × 3.00 mm)

Description

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 andY0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions. The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C. For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference. The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 andY0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions. The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from −40°C to 85°C. For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected to the unused input as a common-mode voltage reference.