CDCM61004 Series

1:4 ultra-low jitter crystal-in clock generator

Catalog

1:4 ultra-low jitter crystal-in clock generator

Part	Ratio - Input:Output	Output	Type	Divider/Multiplier	PLL	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Number of Circuits	Operating Temperature [Max]	Operating Temperature [Min]	Differential - Input:Output	Mounting Type	Frequency - Max [Max]	Package / Case	Input
Texas Instruments CDCM61004RHBR	1:5	LVCMOS LVDS LVPECL	Clock Generator	Yes/No	Yes with Bypass	3.6 V	3 V	32-VQFN (5x5)	1	85 °C	-40 °C	No/Yes	Surface Mount	683.27 MHz	32-VFQFN Exposed Pad	Crystal LVCMOS

Catalog

1:4 ultra-low jitter crystal-in clock generator

Key Features

• One Crystal/LVCMOS Reference InputIncluding 24.8832 MHz, 25 MHz, and 26.5625 MHzInput Frequency Range: 21.875 MHz to28.47 MHzOn-Chip VCO Operates in Frequency Range of1.75 GHz to 2.05 GHz4x Output Available:Pin-Selectable Between LVPECL, LVDS, or2-LVCMOS; Operates at 3.3 VLVCMOS Bypass Output AvailableOutput Frequency Selectable by /1, /2, /3, /4, /6,/8 from a Single Output DividerSupports Common LVPECL/LVDS OutputFrequencies:62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,100 MHz, 106.25 MHz, 125 MHz, 150 MHz,155.52 MHz, 156.25 MHz, 159.375 MHz,187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,311.04 MHz, 312.5 MHz, 622.08 MHz,625 MHzSupports Common LVCMOS Output Frequencies:62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,100 MHz, 106.25 MHz, 125 MHz, 150 MHz,155.52 MHz, 156.25 MHz, 159.375 MHz,187.5 MHz, 200 MHz, 212.5 MHz, 250 MHzOutput Frequency Range: 43.75 MHz to683.264 MHzInternal PLL Loop Bandwidth: 400 kHzHigh-Performance PLL Core:Phase Noise typically at –146 dBc/Hz at5-MHz Offset for 625-MHz LVPECL OutputRandom Jitter typically at 0.509 ps, RMS(10 kHz to 20 MHz) for 625-MHz LVPECL OutputOutput Duty Cycle Corrected to 50% (± 5%)Low Output Skew of 30 ps on LVPECL OutputsDivider Programming Using Control Pins:Two Pins for Prescaler/Feedback DividerThree Pins for Output DividerTwo Pins for Output SelectChip Enable Control Pin Available3.3-V Core and I/O Power SupplyIndustrial Temperature Range: –40°C to 85°C5-mm × 5-mm, 32-pin, VQFN (RHB) PackageESD Protection Exceeds 2 kV (HBM)One Crystal/LVCMOS Reference InputIncluding 24.8832 MHz, 25 MHz, and 26.5625 MHzInput Frequency Range: 21.875 MHz to28.47 MHzOn-Chip VCO Operates in Frequency Range of1.75 GHz to 2.05 GHz4x Output Available:Pin-Selectable Between LVPECL, LVDS, or2-LVCMOS; Operates at 3.3 VLVCMOS Bypass Output AvailableOutput Frequency Selectable by /1, /2, /3, /4, /6,/8 from a Single Output DividerSupports Common LVPECL/LVDS OutputFrequencies:62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,100 MHz, 106.25 MHz, 125 MHz, 150 MHz,155.52 MHz, 156.25 MHz, 159.375 MHz,187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,311.04 MHz, 312.5 MHz, 622.08 MHz,625 MHzSupports Common LVCMOS Output Frequencies:62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,100 MHz, 106.25 MHz, 125 MHz, 150 MHz,155.52 MHz, 156.25 MHz, 159.375 MHz,187.5 MHz, 200 MHz, 212.5 MHz, 250 MHzOutput Frequency Range: 43.75 MHz to683.264 MHzInternal PLL Loop Bandwidth: 400 kHzHigh-Performance PLL Core:Phase Noise typically at –146 dBc/Hz at5-MHz Offset for 625-MHz LVPECL OutputRandom Jitter typically at 0.509 ps, RMS(10 kHz to 20 MHz) for 625-MHz LVPECL OutputOutput Duty Cycle Corrected to 50% (± 5%)Low Output Skew of 30 ps on LVPECL OutputsDivider Programming Using Control Pins:Two Pins for Prescaler/Feedback DividerThree Pins for Output DividerTwo Pins for Output SelectChip Enable Control Pin Available3.3-V Core and I/O Power SupplyIndustrial Temperature Range: –40°C to 85°C5-mm × 5-mm, 32-pin, VQFN (RHB) PackageESD Protection Exceeds 2 kV (HBM)

Description

The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package. The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the1.75 GHz to 2.05 GHz range. The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off. The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN. The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins.CDCM61004 Block Diagramshows a high-level diagram of the CDCM61004. The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C. The CDCM61004 is a highly versatile, low-jitter frequency synthesizer capable of generating four low-jitter clock outputs, selectable between low-voltage positive emitter coupled logic (LVPECL), low-voltage differential signaling (LVDS), or low-voltage complementary metal oxide semiconductor (LVCMOS) outputs, from a low-frequency crystal of LVCMOS input for a variety of wireline and data communication applications. The CDCM61004 features an onboard PLL that can be easily configured solely through control pins. The overall output random jitter performance is less than 1 ps, RMS (from 10 kHz to 20 MHz), making this device a perfect choice for use in demanding applications such as SONET, Ethernet, Fibre Channel, and SAN. The CDCM61004 is available in a small, 32-pin, 5-mm × 5-mm VQFN package. The CDCM61004 is a high-performance, low-phase noise, fully-integrated voltage-controlled oscillator (VCO) clock synthesizer with four universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS bypass output clock is available in an output configuration which can help with crystal loading to achieve an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the1.75 GHz to 2.05 GHz range. The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a low-frequency crystal. The output share an output divider sourced from the VCO core. All device settings are managed through a control pin structure, which has two pins that control the prescaler and feedback divider, three pins that control the output divider, two pins that control the output type, and one pin that controls the output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider) are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividers are turned off. The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output divider, and VCO frequency set fOUTwith respect to fIN. The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also through the use of control pins.CDCM61004 Block Diagramshows a high-level diagram of the CDCM61004. The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.