CD74AC161Synchronous Presettable Binary Counters with Asynchronous Reset | Counters, Dividers | 2 | Active | The ’AC161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting.
The ’AC161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting. |
CD74AC163Synchronous Presettable Binary Counters with Synchronous Reset | Counters, Dividers | 2 | Active | The ’AC163 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is synchronous. A low level at the clear (CLR)\ input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QAhigh). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The ’AC163 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is synchronous. A low level at the clear (CLR)\ input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QAhigh). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. |
CD74AC1648-Bit Serial-In/Parallel-Out Shift Register | Logic | 1 | Obsolete | The ’AC164 and ’ACT164 are 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Advanced CMOS Logic technology.
The ’AC164 and ’ACT164 are 8-bit serial-in/parallel-out shift registers with asynchronous reset that utilize Advanced CMOS Logic technology. |
| Integrated Circuits (ICs) | 4 | Active | The CD74AC174 is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input and is designed for 1.5V to 5.5V VCC operation.
The CD74AC174 is a positive-edge-triggered D-type flip-flop with a direct clear (CLR) input and is designed for 1.5V to 5.5V VCC operation. |
| Flip Flops | 7 | Active | This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features complementary outputs from each flip-flop.
This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features complementary outputs from each flip-flop. |
CD74AC202-ch, 4-input, 1.5-V to 5.5-V NAND gates | Gates and Inverters | 6 | Active | The AC device contains two independent 4-input NAND gates. This device performs the Boolean function Y = (A • B • C • D)\ or Y = A\ + B\ + C\ + D\ in positive logic.
The AC device contains two independent 4-input NAND gates. This device performs the Boolean function Y = (A • B • C • D)\ or Y = A\ + B\ + C\ + D\ in positive logic. |
CD74AC245Octal Non-Inverting Bus Transceivers with 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 12 | Active | The ’AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
The ’AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. |
CD74AC2518-Input Multiplexer with 3-State Outputs | Signal Switches, Multiplexers, Decoders | 4 | Active | The CD74AC251 8-input multiplexers that utilize the Harris Advanced CMOS Logic technology. This multiplexer features both true (Y) and complement (Y) outputs as well as an Output Enable (OE) input. The OE must be at a LOW logic level to enable this device. When the OE input is HIGH, both outputs are in the high-impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and Y outputs.
The CD74AC251 8-input multiplexers that utilize the Harris Advanced CMOS Logic technology. This multiplexer features both true (Y) and complement (Y) outputs as well as an Output Enable (OE) input. The OE must be at a LOW logic level to enable this device. When the OE input is HIGH, both outputs are in the high-impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and Y outputs. |
CD74AC253Dual 4-Input Multiplexers with 3-State Outputs | Integrated Circuits (ICs) | 2 | Active | The CD74AC253 and ’ACT253 dual 4-input multiplexers that utilize Advanced CMOS Logic technology. One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Output Enable (1OE\ or 2OE\) is HIGH, the output is in the high-impedance state.
The CD74AC253 and ’ACT253 dual 4-input multiplexers that utilize Advanced CMOS Logic technology. One of the four sources for each section is selected by the common Select inputs, S0 and S1. When the Output Enable (1OE\ or 2OE\) is HIGH, the output is in the high-impedance state. |
CD74AC257Quad 2-Input Non-Inverting Multiplexers with 3-State Outputs | Logic | 1 | Active | The ’AC257, ’ACT257 and CD74ACT258 are quad 2-input multiplexers with three-state outputs that utilize Advanced CMOS Logic technology.
The ’AC257, ’ACT257 and CD74ACT258 are quad 2-input multiplexers with three-state outputs that utilize Advanced CMOS Logic technology. |
