Texas Instruments

The RCA CD54/74AC646 and CD54/74AC648 and the CD54/74ACT646 and CD54/74ACT648 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC648 and CD54/74ACT648 have inverting outputs. The CD54/74AC646 and CD54/74ACT646 have non-inverting outputs. These devices are bus transceivers with D-type flip-flops which act as internal storage registers on the LOW-to-HIGH transition of either CAB or CBA clock inputs. Output Enable (OE\) and Direction (DIR) inputs control the transceiver functions. Data present at the high-impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The Select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The Direction control determines which data bus will receive data when the Output Enable (OE\) is LOW. In the high-impednace mode (Output Enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the Direction (DIR) and Output Enable (OE\) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time. The CD74AC/ACT646 and CD74AC/ACT648 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commercial (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C). The CD54/ACT646 and CD54AC/ACT648, available in chip form (H suffix), are operable over the -55 to +125°C temperature range. The RCA CD54/74AC646 and CD54/74AC648 and the CD54/74ACT646 and CD54/74ACT648 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC648 and CD54/74ACT648 have inverting outputs. The CD54/74AC646 and CD54/74ACT646 have non-inverting outputs. These devices are bus transceivers with D-type flip-flops which act as internal storage registers on the LOW-to-HIGH transition of either CAB or CBA clock inputs. Output Enable (OE\) and Direction (DIR) inputs control the transceiver functions. Data present at the high-impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The Select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The Direction control determines which data bus will receive data when the Output Enable (OE\) is LOW. In the high-impednace mode (Output Enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the Direction (DIR) and Output Enable (OE\) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time. The CD74AC/ACT646 and CD74AC/ACT648 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commercial (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C). The CD54/ACT646 and CD54AC/ACT648, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

The RCA CD54/74AC651 and CD54/74AC652 and the CD54/74ACT651 and CD54/74ACT652 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC651 and CD54/74ACT651 have inverting outputs. The CD54/74AC562 and CD54/74ACT652 have non-inverting outputs. These devices consist of bus tranceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEABand OE\BAare provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data, and a HIGH selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the octal-bus transceivers and registers. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEABand OE\BA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are a high impedance, each set of bus lines will remain at its last state. The CD74AC/ACT651 and CD74AC/ACT652 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package ty0es are operable over the following temperature ranges. Commerical (0 to 70°C); industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C). The CD54AC/ACT651 and CD54AC/ACT652, available in chip form (H suffix), are operable over the -55 to +125°C temperature range. The RCA CD54/74AC651 and CD54/74AC652 and the CD54/74ACT651 and CD54/74ACT652 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC651 and CD54/74ACT651 have inverting outputs. The CD54/74AC562 and CD54/74ACT652 have non-inverting outputs. These devices consist of bus tranceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEABand OE\BAare provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data, and a HIGH selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the octal-bus transceivers and registers. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEABand OE\BA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are a high impedance, each set of bus lines will remain at its last state. The CD74AC/ACT651 and CD74AC/ACT652 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package ty0es are operable over the following temperature ranges. Commerical (0 to 70°C); industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C). The CD54AC/ACT651 and CD54AC/ACT652, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

The ’ACT02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A\ • B\ or Y = (A + B)\ in positive logic. The ’ACT02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A\ • B\ or Y = (A + B)\ in positive logic.

The SNx4ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean functions Y = A • B or Y = A + B in positive logic. The SNx4ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean functions Y = A • B or Y = A + B in positive logic.

The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The ’ACT138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. The ’ACT138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding.

The ’ACT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. The ’ACT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G)\ inputs are provided for each of the two 4-line sections. Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G)\ inputs are provided for each of the two 4-line sections.

This quadruple 2-line to 1-line data selector/multiplexer is designed for 4.5V to 5.5V VCC operation. This quadruple 2-line to 1-line data selector/multiplexer is designed for 4.5V to 5.5V VCC operation.