CD74AC024-ch, 2-input, 1.5-V to 5.5-V NOR gates | Integrated Circuits (ICs) | 6 | Active | The ’AC02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A•B or Y = A + B in positive logic.
The ’AC02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A•B or Y = A + B in positive logic. |
CD74AC058-ch, 1.5-V to 5.5-V inverters with open-drain outputs | Integrated Circuits (ICs) | 3 | Active | The ’AC05 devices contain six independent inverters. These devices perform the Boolean function Y = A. The open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
The ’AC05 devices contain six independent inverters. These devices perform the Boolean function Y = A. The open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. |
CD74AC109Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | Logic | 2 | Active | The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications. |
CD74AC112Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Logic | 3 | Active | The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. |
CD74AC1383-Line to 8-Line inverting decoders/demultiplexers | Signal Switches, Multiplexers, Decoders | 3 | Active | The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding.
The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. |
CD74AC139Dual 2-to-4 Line Decoder/Demultiplexer | Logic | 2 | Active | The ’AC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 1.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The ’AC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 1.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. |
| Logic | 3 | Active | This data selector/multiplexer provides full binary decoding to select one of eight data sources. The strobe (G) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low.
This data selector/multiplexer provides full binary decoding to select one of eight data sources. The strobe (G) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low. |
| Signal Switches, Multiplexers, Decoders | 4 | Active | Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G) inputs are provided for each of the two 4-line sections.
Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G) inputs are provided for each of the two 4-line sections. |
CD74AC157Quad 2-Input Non-Inverting Multiplexers | Logic | 1 | Active | These quadruple 2-line to 1-line data selectors/multiplexers are designed for 1.5-V to 5.5-V VCCoperation.
The ’AC157 devices feature a common strobe (G)\ input. When the strobe is high, all outputs are low. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The devices provide true data.
These quadruple 2-line to 1-line data selectors/multiplexers are designed for 1.5-V to 5.5-V VCCoperation.
The ’AC157 devices feature a common strobe (G)\ input. When the strobe is high, all outputs are low. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The devices provide true data. |
| Logic | 1 | Active | This quadruple 2-line to 1-line data selector/multiplexer is designed for 1.5-V to 5.5-V VCCoperation.
The CD74AC158 features a common strobe (G)\ input. When the strobe is high, all outputs are high. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. This device provides inverted data.
This quadruple 2-line to 1-line data selector/multiplexer is designed for 1.5-V to 5.5-V VCCoperation.
The CD74AC158 features a common strobe (G)\ input. When the strobe is high, all outputs are high. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. This device provides inverted data. |
