Texas Instruments

The TPS65916 PMIC integrates five configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains five LDOs to power low-current or low-noise domains. The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65916 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response. The TPS65916 PMIC integrates five configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains five LDOs to power low-current or low-noise domains. The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65916 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.

The TPS65917-Q1 PMIC integrates five configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains five LDOs to power low-current or low-noise domains. The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors.As an additional safety feature, the he OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65917-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response. The TPS65917-Q1 PMIC integrates five configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains five LDOs to power low-current or low-noise domains. The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors.As an additional safety feature, the he OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65917-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.

The TPS65919-Q1 PMIC integrates four configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains four LDOs to power low-current or low-noise domains. The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65919-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response. The TPS65919-Q1 PMIC integrates four configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The device is AEC-Q100 qualified. The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains four LDOs to power low-current or low-noise domains. The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS65919-Q1 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.

The TPS65921 device is a highly integrated power-management circuit (IC) that supports the power and peripheral requirements of the OMAP application processors. The device contains power management, a universal serial bus (USB) high-speed (HS) transceiver, an analog-to-digital converter (ADC), a real-time clock (RTC), a keypad interface, and an embedded power control (EPC). The power portion of the device contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple low-dropout (LDO) regulators, an EPC to manage the power-sequencing requirements of OMAP, and an RTC module. The USB module provides an HS 2.0 transceiver suitable for direct connection to the OMAP universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump (CP). The device also provides auxiliary modules: ADC, keypad interface, and general-purpose inputs/outputs (GPIOs) muxed with the JTAG functions. The keypad interface implements a built-in scanning algorithm to decode hardware-based key presses and to reduce software use, with multiple additional GPIOs that can be used as interrupts when they are configured as inputs. The TPS65921 device is a highly integrated power-management circuit (IC) that supports the power and peripheral requirements of the OMAP application processors. The device contains power management, a universal serial bus (USB) high-speed (HS) transceiver, an analog-to-digital converter (ADC), a real-time clock (RTC), a keypad interface, and an embedded power control (EPC). The power portion of the device contains three buck converters, two controllable by a dedicated SmartReflex class-3 interface, multiple low-dropout (LDO) regulators, an EPC to manage the power-sequencing requirements of OMAP, and an RTC module. The USB module provides an HS 2.0 transceiver suitable for direct connection to the OMAP universal transceiver macrocell interface (UTMI) + low pin interface (ULPI) with an integrated charge pump (CP). The device also provides auxiliary modules: ADC, keypad interface, and general-purpose inputs/outputs (GPIOs) muxed with the JTAG functions. The keypad interface implements a built-in scanning algorithm to decode hardware-based key presses and to reduce software use, with multiple additional GPIOs that can be used as interrupts when they are configured as inputs.

The TPS6593-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I 2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. The TPS6593-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I 2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6593-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6593-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response.

The TPS6594-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6594-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6594-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply , input over-voltage protection, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6594-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response. The TPS6594-Q1 device provides four flexible multi-phase configurable BUCK regulators with 3.5 A output current per phase, and one additional BUCK regulator with 2 A output current. All of the BUCK regulators can be synchronized to an internal 2.2-MHz or 4.4-MHz or an external 1-MHz, 2-MHz, or 4-MHz clock signal. To improve the EMC performance, an integrated spread-spectrum modulation can be added to the synchronized BUCK switching clock signal. This clock signal can also be made available to external devices through a GPIO output pin. The device provides four LDOs: three with 500-mA capability, which can be configured as load switches; one with 300-mA capability and low-noise performance. Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external programming. Most static configurations, stored in the register map of the device, can be changed from the default through SPI or I2C interfaces to configure the device to meet many different system needs. The NVM contains a bit-integrity-error detection feature (CRC) to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state. The TPS6594-Q1 includes a 32-kHz crystal oscillator, which generates an accurate 32-kHz clock for the integrated RTC module. A backup-battery management provides power to the crystal oscillator and the real-time clock (RTC) module from a coin cell battery or a super-cap in the event of power loss from the main supply. The TPS6594-Q1 device includes protection and diagnostic mechanisms such as voltage monitoring on the input supply , input over-voltage protection, voltage monitoring on all BUCK and LDO regulator outputs, register and interface CRC, current-limit, short-circuit protection, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6594-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response.