THS8135Triple 10-bit 240MSPS video DAC with tri-level sync & video (ITU-R.BT601)-compliant full scale range | Data Acquisition | 1 | Unknown | The THS8135 is a general-purpose triple high-speed D/A converter optimized for use in video/graphics applications. The device operates from 3.3-V analog and 1.8-V digital supplies. The THS8135 performance is assured at a sampling rate up to 240 MSPS. The THS8135 consists of three 10-bit D/A converters and additional circuitry for bi-level/tri-level sync and blanking level generation. By providing a dc offset for the lowest video amplitude output in video DAC mode, the device can insert a (negative) bi-level or (negative/positive) tri-level sync on either only the green/luminance (sync-on-green/sync-on-Y) channel or on all channels for video applications. A generic DAC mode avoids this dc offset, making this device suitable for non-video applications as well.
The THS8135 is a footprint-compatible functional upgrade to the THS8133. In addition, the THS8135 allows a higher update rate for oversampled video digitizing for all PC graphics formats up to UXGA (1600x1200) resolution at 85 Hz and all practical digital TV formats including HDTV. The support for oversampling significantly reduces the complexity of the analog reconstruction filter required behind the DAC.
Standard video levels can be generated for the full 10-bit input code range. Alternatively, the same levels can be reached from a reduced input code range compliant to the video sampling standard ITU-R.BT-601. In that case, the full-scale range of the DAC is dependent on the RGB or YCbCr color space configuration of the device. When configured for RGB operation, full video output swing is reached for input codes 64-940 on all channels. When configured for YCbCr operation, code range 64-940 on Y and code range 64-960 on Cb and Cr channels generate full output swing using internal amplitude scaling on these color components. The device provides headroom to accommodate under-/over-shoot outside the ITU-R.BT601 range to allow the generation of ITU-R.BT601 illegal colors or super-black / super-white levels.
A digital control input for insertion of a reference (blanking) level on the analog outputs is included. The amplitude of the blanking level is configurable for either RGB or YPbPr component outputs and for full or reduced input code ranges. The inserted sync output amplitude(s) always has the required 7:3 ratio to the full-scale video amplitude.
The current-steering DACs can be directly terminated in resistive loads to produce voltage outputs. The device provides a flexible configuration of maximum output current drive. The devices output drivers have been specifically designed to produce standard video output levels when directly connected to a single-ended double-terminated 75-Ω coaxial cable.
The input data format can be either 3x10 bit 4:4:4, 2x10 bit 4:2:2, or 1x10 bit 4:2:2. This enables a direct interface to a wide range of video DSP/ASICs including parts generating ITU-R.BT656 formatted output data. However, the THS8135 needs specific input synchronization signals to properly insert a composite sync onto its outputs as it does not extract embedded SAV/EAV synchronization codes from the ITU-R.BT656 input. Along with other extra functionality, this feature is available on a derivative device (THS8200).
The THS8135 is a general-purpose triple high-speed D/A converter optimized for use in video/graphics applications. The device operates from 3.3-V analog and 1.8-V digital supplies. The THS8135 performance is assured at a sampling rate up to 240 MSPS. The THS8135 consists of three 10-bit D/A converters and additional circuitry for bi-level/tri-level sync and blanking level generation. By providing a dc offset for the lowest video amplitude output in video DAC mode, the device can insert a (negative) bi-level or (negative/positive) tri-level sync on either only the green/luminance (sync-on-green/sync-on-Y) channel or on all channels for video applications. A generic DAC mode avoids this dc offset, making this device suitable for non-video applications as well.
The THS8135 is a footprint-compatible functional upgrade to the THS8133. In addition, the THS8135 allows a higher update rate for oversampled video digitizing for all PC graphics formats up to UXGA (1600x1200) resolution at 85 Hz and all practical digital TV formats including HDTV. The support for oversampling significantly reduces the complexity of the analog reconstruction filter required behind the DAC.
Standard video levels can be generated for the full 10-bit input code range. Alternatively, the same levels can be reached from a reduced input code range compliant to the video sampling standard ITU-R.BT-601. In that case, the full-scale range of the DAC is dependent on the RGB or YCbCr color space configuration of the device. When configured for RGB operation, full video output swing is reached for input codes 64-940 on all channels. When configured for YCbCr operation, code range 64-940 on Y and code range 64-960 on Cb and Cr channels generate full output swing using internal amplitude scaling on these color components. The device provides headroom to accommodate under-/over-shoot outside the ITU-R.BT601 range to allow the generation of ITU-R.BT601 illegal colors or super-black / super-white levels.
A digital control input for insertion of a reference (blanking) level on the analog outputs is included. The amplitude of the blanking level is configurable for either RGB or YPbPr component outputs and for full or reduced input code ranges. The inserted sync output amplitude(s) always has the required 7:3 ratio to the full-scale video amplitude.
The current-steering DACs can be directly terminated in resistive loads to produce voltage outputs. The device provides a flexible configuration of maximum output current drive. The devices output drivers have been specifically designed to produce standard video output levels when directly connected to a single-ended double-terminated 75-Ω coaxial cable.
The input data format can be either 3x10 bit 4:4:4, 2x10 bit 4:2:2, or 1x10 bit 4:2:2. This enables a direct interface to a wide range of video DSP/ASICs including parts generating ITU-R.BT656 formatted output data. However, the THS8135 needs specific input synchronization signals to properly insert a composite sync onto its outputs as it does not extract embedded SAV/EAV synchronization codes from the ITU-R.BT656 input. Along with other extra functionality, this feature is available on a derivative device (THS8200). |
THS8136Triple 10-bit 180-MSPS graphics and video DAC | ADCs/DACs - Special Purpose | 3 | Active | The THS8136 is a general-purpose triple high-speed digital-to-analog (D/A) converter optimized for use in video/graphics applications. The device operates from 3.3-V analog and 1.8-V digital supplies with D/A converter performance assured at sampling rates up to 180 MHz. The THS8136 consists of three 10-bit D/A converters and additional circuitry for bi-level sync and blanking level generation. The current-steering DACs have been specifically designed to produce standard video output levels when directly connected to a single-ended double-terminated 75-Ω coaxial cable.
By providing a dc offset in sync insertion mode, the THS8136 can generate a bi-level sync on the AG DAC output without sacrificing DAC resolution. Support is also provided for insertion of RGB or YPbPr reference or blanking levels, irrespective of the DAC input codes. A generic DAC mode is provided for applications not requiring sync generation. All digital inputs are 1.8-V compatible.
The THS8136 is a general-purpose triple high-speed digital-to-analog (D/A) converter optimized for use in video/graphics applications. The device operates from 3.3-V analog and 1.8-V digital supplies with D/A converter performance assured at sampling rates up to 180 MHz. The THS8136 consists of three 10-bit D/A converters and additional circuitry for bi-level sync and blanking level generation. The current-steering DACs have been specifically designed to produce standard video output levels when directly connected to a single-ended double-terminated 75-Ω coaxial cable.
By providing a dc offset in sync insertion mode, the THS8136 can generate a bi-level sync on the AG DAC output without sacrificing DAC resolution. Support is also provided for insertion of RGB or YPbPr reference or blanking levels, irrespective of the DAC input codes. A generic DAC mode is provided for applications not requiring sync generation. All digital inputs are 1.8-V compatible. |
| ADCs/DACs - Special Purpose | 1 | Obsolete | |
THS8200-EPEnhanced Product Triple 10-Bit All Format Video DAC | Integrated Circuits (ICs) | 2 | Active | THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.
THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3×10-bit, 2×10-bit or 1×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in which it requests video data from an external (memory) source.
THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully-programmable 3×3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2× oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.
The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video (1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves 100% of the DAC’s 11-bit dynamic range for video data.
THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.
THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.
THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3×10-bit, 2×10-bit or 1×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in which it requests video data from an external (memory) source.
THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully-programmable 3×3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2× oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.
The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video (1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves 100% of the DAC’s 11-bit dynamic range for video data.
THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification. |
| RF and Wireless | 2 | Obsolete | |
THS900050 MHz to 750 MHz Cascadable Amplifier | RF and Wireless | 1 | Active | The THS9000 is a medium power, cascadeable, gain block optimized for high IF frequencies. The amplifier incorporates internal impedance matching to 50 Ω. The part mounted on the standard EVM achieves greater than 15-dB input and output return loss from 50 MHz to 325 MHz with VS= 5 V, R(BIAS)= 237 Ω, L(COL)= 470 nH. Design requires only two dc-blocking capacitors, one power-supply bypass capacitor, one RF choke, and one bias resistor.
The THS9000 is a medium power, cascadeable, gain block optimized for high IF frequencies. The amplifier incorporates internal impedance matching to 50 Ω. The part mounted on the standard EVM achieves greater than 15-dB input and output return loss from 50 MHz to 325 MHz with VS= 5 V, R(BIAS)= 237 Ω, L(COL)= 470 nH. Design requires only two dc-blocking capacitors, one power-supply bypass capacitor, one RF choke, and one bias resistor. |
| RF Amplifiers | 2 | Active | |
THVD133032-Mbps 3.3-V half-duplex RS485 transceiver with IEC ESD protection | Drivers, Receivers, Transceivers | 1 | Active | THVD1330 is a robust half-duplex RS-485 transceiver for industrial applications. The bus pins are immune to high levels of IEC Contact Discharge ESD events eliminating the need of additional system level protection components. Both the transmitter and receiver are capable of operating at maximum 32 Mbps signaling rate. The device is optimized for small propagation delay variation to support time-sensitive applications such as Baseband unit (BBU) and Remote radio unit (RRU).
The device operates from a single 3.3 V supply. The wide common-mode voltage range and low input leakage on bus pins make THVD1330 suitable for multi-point applications over long cable runs.
THVD1330 is available in industry standard 8-pin SOIC package for drop-in compatibility. The device is characterized from –40°C to 125°C.
THVD1330 is a robust half-duplex RS-485 transceiver for industrial applications. The bus pins are immune to high levels of IEC Contact Discharge ESD events eliminating the need of additional system level protection components. Both the transmitter and receiver are capable of operating at maximum 32 Mbps signaling rate. The device is optimized for small propagation delay variation to support time-sensitive applications such as Baseband unit (BBU) and Remote radio unit (RRU).
The device operates from a single 3.3 V supply. The wide common-mode voltage range and low input leakage on bus pins make THVD1330 suitable for multi-point applications over long cable runs.
THVD1330 is available in industry standard 8-pin SOIC package for drop-in compatibility. The device is characterized from –40°C to 125°C. |
THVD14003.3-V to 5-V, 500-Kbps, RS-485 transceiver in small package option with ±12-kV IEC ESD pro | Interface | 2 | Active | THVD1400 and THVD1420 are robust half-duplex RS-485 transceivers for industrial applications. The bus pins are immune to high levels of IEC Contact Discharge ESD events, eliminating the need for additional system level protection components.
The devices operate from a single 3 to 5.5-V supply. The wide common-mode voltage range and low input leakage on bus pins make the devices suitable for multi-point applications over long cable runs.
THVD1400 and THVD1420 are available in industry standard, 8-pin SOIC package for drop-in compatibility as well as in the industry-leading, small SOT package. The devices are characterized for ambient temperatures from –40°C to 125°C.
THVD1400 and THVD1420 are robust half-duplex RS-485 transceivers for industrial applications. The bus pins are immune to high levels of IEC Contact Discharge ESD events, eliminating the need for additional system level protection components.
The devices operate from a single 3 to 5.5-V supply. The wide common-mode voltage range and low input leakage on bus pins make the devices suitable for multi-point applications over long cable runs.
THVD1400 and THVD1420 are available in industry standard, 8-pin SOIC package for drop-in compatibility as well as in the industry-leading, small SOT package. The devices are characterized for ambient temperatures from –40°C to 125°C. |
THVD1400V3-V to 5.5-V half-duplex RS-485 transceiver with flexible I/O and slew rate control | Integrated Circuits (ICs) | 1 | Active | Separate logic supply pin eliminates the need for an additional level shifter when the MCU and RS-485 transceivers are operating with different supplies. The bus pins are immune to high levels of IEC Contact Discharge ESD events eliminating the need for additional system level protection components. The wide common-mode voltage range and low input leakage on bus pins makes the device suitable for multi-point applications over long cable runs.
THVD1400V is available in space-saving thermally efficient 10-VSON package (3 mm x 3 mm). The device is characterized for ambient temperature from –40°C to 125°C.
Separate logic supply pin eliminates the need for an additional level shifter when the MCU and RS-485 transceivers are operating with different supplies. The bus pins are immune to high levels of IEC Contact Discharge ESD events eliminating the need for additional system level protection components. The wide common-mode voltage range and low input leakage on bus pins makes the device suitable for multi-point applications over long cable runs.
THVD1400V is available in space-saving thermally efficient 10-VSON package (3 mm x 3 mm). The device is characterized for ambient temperature from –40°C to 125°C. |
