Catalog
Enhanced Product Triple 10-Bit All Format Video DAC
Key Features
• Three 11-Bit 205-MSPS D/A Converters With IntegratedBi-Level/Tri-Level Sync InsertionSupport for All ATSC Video Formats (Including 1080P) andPC Graphics Formats (Up to UXGA at 75 Hz)INPUTFlexible 10/15/16/20/24/30-Bit Digital Video Input InterfaceWith Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 SampledVideo Synchronization Via Hsync, Vsync Dedicated Inputs or ViaExtraction of Embedded SAV/EAV Codes According to ITU-R.BT601(SDTV) or SMPTE274M/SMPTE296M (HDTV)Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can ReceiveVideo-Over-DVI Formats According to the EIA-861 Specification andConvert to YPbPr/RGB Component Formats With Separate Syncs orEmbedded Composite SyncVIDEO PROCESSINGProgrammable Clip/Shift/Multiply Function for Operation WithFull-Range or ITU-R.BT601 Video Range Input DataProgrammable Digital Fine-Gain Controller on Each Analog OutputChannel, for Accurate Channel Matching and ProgrammableWhite-Balance ControlBuilt-In 4:2:2 to 4:4:4 Video Interpolation FilterBuilt-In 2× Oversampling SDTV/HDTV InterpolationFilter for Improved Video Frequency CharacteristicFully Programmable Digital Color Space Conversion CircuitFully Programmable Display Timing Generator to Supply AllSDTV and HDTV Composite Sync Ttiming Formats, Progressiveand InterlacedFully Programmable Hsync/Vsync OutputsVertical Blanking Interval (VBI) Override or Data Pass-Thrufor VBI Data TransparencyProgrammable CGMS Data Generation and InsertionOUTPUTDigitalITU-R BT.656 Digital Video Output PortAnalogAnalog Component Output from Software-Switchable700-mV/1.3-V Compliant Output DACs at 37.5-loadProgrammable Video/Sync Ratio (7:3 or 10:4)Programmable Video PedestalGENERALBuilt-In Video Color Bar Test Pattern GeneratorFast Mode I2C Control InterfaceConfigurable Master or Slave Timing ModeConfiguration Modes Allow the Device to Act as aMaster Timing Source for Requesting Data from, e.g.,the Video Frame Buffer. Alternatively, the Device CanSlave to an External Timing Master (Master Mode OnlyAvailable for PC Graphics Output Modes).DAC and Chip Powerdown ModesLow-Power 1.8-/3.3-V Operation80-pin PowerPAD™ Plastic Quad Flatpack Package withEfficient Heat Dissipation and Small Physical SizeAPPLICATIONSDVD PlayersDigital-TV/Interactive-TV/Internet Set-Top BoxesPersonal Video RecordersHDTV Display or Projection Systemsdigital Video SystemsPowerPAD Is a trademark of Texas Instruments.Three 11-Bit 205-MSPS D/A Converters With IntegratedBi-Level/Tri-Level Sync InsertionSupport for All ATSC Video Formats (Including 1080P) andPC Graphics Formats (Up to UXGA at 75 Hz)INPUTFlexible 10/15/16/20/24/30-Bit Digital Video Input InterfaceWith Support for YCbCr or RGB Data, Either 4:4:4 or 4:2:2 SampledVideo Synchronization Via Hsync, Vsync Dedicated Inputs or ViaExtraction of Embedded SAV/EAV Codes According to ITU-R.BT601(SDTV) or SMPTE274M/SMPTE296M (HDTV)Glueless Interface to TI DVI 1.0 (With HDCP) Receivers. Can ReceiveVideo-Over-DVI Formats According to the EIA-861 Specification andConvert to YPbPr/RGB Component Formats With Separate Syncs orEmbedded Composite SyncVIDEO PROCESSINGProgrammable Clip/Shift/Multiply Function for Operation WithFull-Range or ITU-R.BT601 Video Range Input DataProgrammable Digital Fine-Gain Controller on Each Analog OutputChannel, for Accurate Channel Matching and ProgrammableWhite-Balance ControlBuilt-In 4:2:2 to 4:4:4 Video Interpolation FilterBuilt-In 2× Oversampling SDTV/HDTV InterpolationFilter for Improved Video Frequency CharacteristicFully Programmable Digital Color Space Conversion CircuitFully Programmable Display Timing Generator to Supply AllSDTV and HDTV Composite Sync Ttiming Formats, Progressiveand InterlacedFully Programmable Hsync/Vsync OutputsVertical Blanking Interval (VBI) Override or Data Pass-Thrufor VBI Data TransparencyProgrammable CGMS Data Generation and InsertionOUTPUTDigitalITU-R BT.656 Digital Video Output PortAnalogAnalog Component Output from Software-Switchable700-mV/1.3-V Compliant Output DACs at 37.5-loadProgrammable Video/Sync Ratio (7:3 or 10:4)Programmable Video PedestalGENERALBuilt-In Video Color Bar Test Pattern GeneratorFast Mode I2C Control InterfaceConfigurable Master or Slave Timing ModeConfiguration Modes Allow the Device to Act as aMaster Timing Source for Requesting Data from, e.g.,the Video Frame Buffer. Alternatively, the Device CanSlave to an External Timing Master (Master Mode OnlyAvailable for PC Graphics Output Modes).DAC and Chip Powerdown ModesLow-Power 1.8-/3.3-V Operation80-pin PowerPAD™ Plastic Quad Flatpack Package withEfficient Heat Dissipation and Small Physical SizeAPPLICATIONSDVD PlayersDigital-TV/Interactive-TV/Internet Set-Top BoxesPersonal Video RecordersHDTV Display or Projection Systemsdigital Video SystemsPowerPAD Is a trademark of Texas Instruments.
Description
AI
THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.
THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3×10-bit, 2×10-bit or 1×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in which it requests video data from an external (memory) source.
THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully-programmable 3×3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2× oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.
The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video (1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves 100% of the DAC’s 11-bit dynamic range for video data.
THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.
THS8200 is a complete video back-end D/A solution for DVD players, personal video recorders and set-top boxes, or any system requiring the conversion of digital component video signals into the analog domain.
THS8200 can accept a variety of digital input formats, in both 4:4:4 and 4:2:2 formats, over a 3×10-bit, 2×10-bit or 1×10-bit interface. The device synchronizes to incoming video data either through dedicated Hsync/Vsync inputs or through extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream. Alternatively, when configured for generating PC graphics output, THS8200 also provides a master timing mode in which it requests video data from an external (memory) source.
THS8200 contains a display timing generator that is completely programmable for all standard and nonstandard video formats up to the maximum supported pixel clock of 205 MSPS. Therefore, the device supports all component video and PC graphics (VESA) formats. A fully-programmable 3×3 matrixing operation is included for color space conversion. All video formats, up to the HDTV 1080I and 720P formats, can also be internally 2× oversampled. Oversampling relaxes the need for sharp external analog reconstruction filters behind the DAC and improves the video frequency characteristic.
The output compliance range can be set via external adjustment resistors and there is a choice of two settings, in order to accommodate without hardware changes both component video/PC graphics (700 mV) and composite video (1.3 V) outputs. An internal programmable clip/shift/multiply function on the video data assures standards-compliant video output ranges for either full 10-bit or reduced ITU-R.BT601 style video input. In order to avoid nonlinearities after scaling of the video range, the DACs are internally of 11-bit resolution. Furthermore, a bi- or tri-level sync with programmable amplitude (in order to support both 700/300-mV and 714/286-mV video/sync ratios) can be inserted either on the green/luma channel only or on all three output channels. This sync insertion is generated from additional current sources in the DACs such that the full DAC resolution remains available for the video range. This preserves 100% of the DAC’s 11-bit dynamic range for video data.
THS8200 optionally supports the pass-through of ancillary data embedded in the input video stream or can insert ancillary data into the 525P analog component output according to the CGMS data specification.
