Texas Instruments

The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow. There is flexible ×9/×18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN)\ inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE)\ input is provided for 3-state control of the outputs. The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin. The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low. Partial reset (PRS)\ also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode existing before partial reset is asserted remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable. A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin. The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode. The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron CMOS technology. For more information on this device family, see the following application reports: The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow. There is flexible ×9/×18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN)\ inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE)\ input is provided for 3-state control of the outputs. The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin. The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low. Partial reset (PRS)\ also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode existing before partial reset is asserted remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable. A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin. The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode. The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron CMOS technology. For more information on this device family, see the following application reports:

The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow. There is flexible ×9/×18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs. The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin. The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low. Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode (existing before partial reset is asserted) remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable. A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin. The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode. The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron CMOS technology. For more information on this device family, see the following application reports: The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow. There is flexible ×9/×18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN)\ inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs. The frequencies of both the RCLK and the WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode in use. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF)\, programmable almost-empty flag (PAE)\, and programmable almost-full flag (PAF)\. The IR\ and OR\ functions are selected in FWFT mode. The EF\ and FF\ functions are selected in standard mode. HF\, PAE\, and PAF\ always are available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings also are provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial or parallel offset loading has been selected. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , PAE\ is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only and not RCLK. The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin. The retransmit function allows data to be reread from the FIFO more than once. A low on the RT\ input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. During master reset (MRS)\, the functions for all the operating modes are programmed. These include FWFT or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode, programmable-flag operating and programming method, programmable-flag default offsets, and interspersed parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected timing mode, EF\ is set low or OR\ is set high and FF\ is set high or IR\ is set low. Also, PAE\ is set low, PAF\ is set high, and HF\ is set high. The Q outputs are set low. Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, default or programmed offset settings, input and output bus widths, big endian/little endian, interspersed parity select, and retransmit mode (existing before partial reset is asserted) remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation when reprogramming programmable flags and other functions would be undesirable. A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE)\ pin. The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input width is set to ×18 mode. The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron CMOS technology. For more information on this device family, see the following application reports:

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits: Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs. The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings are also provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of the FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial parallel offset loading has been selected. During master reset (MRS\), the read and write pointers are set to the first location of the FIFO. The FWFT pin selects standard mode or FWFT mode. Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , the PAE\ is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM). The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT\) input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register, with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit timing. The devices can be configured with different input and output bus widths (see Table 1). A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE\) pin (see Figure 4 for the bus-matching byte arrangement). The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of the offset registers. It does not affect data written to and read from the FIFO. The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C. The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits: Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs. The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings are also provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of the FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial parallel offset loading has been selected. During master reset (MRS\), the read and write pointers are set to the first location of the FIFO. The FWFT pin selects standard mode or FWFT mode. Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , the PAE\ is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM). The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT\) input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register, with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit timing. The devices can be configured with different input and output bus widths (see Table 1). A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE\) pin (see Figure 4 for the bus-matching byte arrangement). The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of the offset registers. It does not affect data written to and read from the FIFO. The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C.

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits: Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs. The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings are also provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of the FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial parallel offset loading has been selected. During master reset (MRS\), the read and write pointers are set to the first location of the FIFO. The FWFT pin selects standard mode or FWFT mode. Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , the PAE\ is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM). The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT\) input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register, with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit timing. The devices can be configured with different input and output bus widths (see Table 1). A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE\) pin (see Figure 4 for the bus-matching byte arrangement). The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of the offset registers. It does not affect data written to and read from the FIFO. The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C. The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits: Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs. The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode. PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings are also provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of the FSEL0, FSEL1, and LD\. For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial parallel offset loading has been selected. During master reset (MRS\), the read and write pointers are set to the first location of the FIFO. The FWFT pin selects standard mode or FWFT mode. Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\. If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK. If the synchronous PAE\/PAF\ configuration is selected , the PAE\ is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM). The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT\) input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency. If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register, with respect to the same RCLK edge that initiated the retransmit, if RT\ is low. See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit timing. The devices can be configured with different input and output bus widths (see Table 1). A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE\) pin (see Figure 4 for the bus-matching byte arrangement). The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of the offset registers. It does not affect data written to and read from the FIFO. The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C.

The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCCoperation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(1)backplane topologies. The SN74VMEH22501A is pin-for-pin capatible to the SN74VMEH22501 (TI literature number SCES357), but operates at a wider operating temperature (−40°C to 85°C) range. High-speed backplane operation is a direct result of the improved OEC™ circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC± 50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane. All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioffcircuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCCcircuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OEandOEBY) inputs should be tied to VCCthrough a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input. The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCCoperation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(1)backplane topologies. The SN74VMEH22501A is pin-for-pin capatible to the SN74VMEH22501 (TI literature number SCES357), but operates at a wider operating temperature (−40°C to 85°C) range. High-speed backplane operation is a direct result of the improved OEC™ circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC± 50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane. All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioffcircuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCCcircuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OEandOEBY) inputs should be tied to VCCthrough a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input.

The SN74VMEH22501A-EP 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCCoperation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(2)backplane topologies. The SN74VMEH22501A-EP device is pin-for-pin compatible to the SN74VMEH22501 device (SCES357), but operates at a wider operating temperature range. High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC±50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-MB transfer rates on linear backplanes and, possibly, 1-GB transfer rates on the VME320 backplane. All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioffcircuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCCcircuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OEandOEBY) inputs should be tied to VCCthrough a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input. The SN74VMEH22501A-EP 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V VCCoperation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic levels and VME64, VME64x, or VME320(2)backplane topologies. The SN74VMEH22501A-EP device is pin-for-pin compatible to the SN74VMEH22501 device (SCES357), but operates at a wider operating temperature range. High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC±50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-MB transfer rates on linear backplanes and, possibly, 1-GB transfer rates on the VME320 backplane. All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioffcircuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCCcircuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, output-enable (OEandOEBY) inputs should be tied to VCCthrough a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this input.

These circuits are TTL-compatible, high-speed line receivers. Each is a monolithic dual circuit featuring two independent channels. They are designed for general use, as well as for such specific applications as data comparators and balanced, unbalanced, and party-line transmission systems. These devices are unilaterally interchangeable with and are replacements for the SN55107, SN75107, and SN75108, but offer diode-clamped strobe inputs to simplify circuit design. The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful in certain party-line systems that have multiple VCC+power supplies and can be operated with some of the VCC+supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows: This would be a problem in specific systems that might have the transmission lines biased to some potential greater than 1.4 V. The SN55107A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN75107A, SN75107B, and SN75108A are characterized for operation from 0°C to 70°C. H = high level, L = low level, X = irrelevant These circuits are TTL-compatible, high-speed line receivers. Each is a monolithic dual circuit featuring two independent channels. They are designed for general use, as well as for such specific applications as data comparators and balanced, unbalanced, and party-line transmission systems. These devices are unilaterally interchangeable with and are replacements for the SN55107, SN75107, and SN75108, but offer diode-clamped strobe inputs to simplify circuit design. The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful in certain party-line systems that have multiple VCC+power supplies and can be operated with some of the VCC+supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows: This would be a problem in specific systems that might have the transmission lines biased to some potential greater than 1.4 V. The SN55107A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN75107A, SN75107B, and SN75108A are characterized for operation from 0°C to 70°C. H = high level, L = low level, X = irrelevant

These circuits are TTL-compatible, high-speed line receivers. Each is a monolithic dual circuit featuring two independent channels. They are designed for general use, as well as for such specific applications as data comparators and balanced, unbalanced, and party-line transmission systems. These devices are unilaterally interchangeable with and are replacements for the SN55107, SN75107, and SN75108, but offer diode-clamped strobe inputs to simplify circuit design. The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful in certain party-line systems that have multiple VCC+power supplies and can be operated with some of the VCC+supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows: This would be a problem in specific systems that might have the transmission lines biased to some potential greater than 1.4 V. The SN55107A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN75107A, SN75107B, and SN75108A are characterized for operation from 0°C to 70°C. H = high level, L = low level, X = irrelevant These circuits are TTL-compatible, high-speed line receivers. Each is a monolithic dual circuit featuring two independent channels. They are designed for general use, as well as for such specific applications as data comparators and balanced, unbalanced, and party-line transmission systems. These devices are unilaterally interchangeable with and are replacements for the SN55107, SN75107, and SN75108, but offer diode-clamped strobe inputs to simplify circuit design. The essential difference between the A and B versions can be seen in the schematics. Input-protection diodes are in series with the collectors of the differential-input transistors of the B versions. These diodes are useful in certain party-line systems that have multiple VCC+power supplies and can be operated with some of the VCC+supplies turned off. In such a system, if a supply is turned off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows: This would be a problem in specific systems that might have the transmission lines biased to some potential greater than 1.4 V. The SN55107A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN75107A, SN75107B, and SN75108A are characterized for operation from 0°C to 70°C. H = high level, L = low level, X = irrelevant

The SN55110A, SN75110A, and SN75112 dual line drivers have improved output current regulation with supply voltage and temperature variations. In addition, the higher current of the SN75112 (27 mA) allows data to be transmitted over longer lines. These drivers offer optimum performance when used with the SN55107A, SN75107A, and SN75108A line receivers. These drivers feature independent channels with common voltage supply and ground terminals. The significant difference between the three drivers is in the output-current specification. The driver circuits feature a constant output current that is switched to either of two output terminals by the appropriate logic levels at the input terminals. The output current can be switched off (inhibited) by low logic levels on the enable inputs. The output current is nominally 12 mA for the '110A devices, and is 27 mA for the SN75112. The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output current in the inhibited mode, IO(off), is specified so that minimum line loading is induced when the driver is used in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high. The output impedance of a transistor is biased to cutoff. The driver outputs have a common-mode voltage range of –3 V to 10 V, allowing common-mode voltage on the line without affecting driver performance. All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at 2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure 400-mV noise margin when interfaced with TTL Series 54/74. The SN55110A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN75110A and SN75112 are characterized for operation from 0°C to 70°C. The SN55110A, SN75110A, and SN75112 dual line drivers have improved output current regulation with supply voltage and temperature variations. In addition, the higher current of the SN75112 (27 mA) allows data to be transmitted over longer lines. These drivers offer optimum performance when used with the SN55107A, SN75107A, and SN75108A line receivers. These drivers feature independent channels with common voltage supply and ground terminals. The significant difference between the three drivers is in the output-current specification. The driver circuits feature a constant output current that is switched to either of two output terminals by the appropriate logic levels at the input terminals. The output current can be switched off (inhibited) by low logic levels on the enable inputs. The output current is nominally 12 mA for the '110A devices, and is 27 mA for the SN75112. The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output current in the inhibited mode, IO(off), is specified so that minimum line loading is induced when the driver is used in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high. The output impedance of a transistor is biased to cutoff. The driver outputs have a common-mode voltage range of –3 V to 10 V, allowing common-mode voltage on the line without affecting driver performance. All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at 2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure 400-mV noise margin when interfaced with TTL Series 54/74. The SN55110A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN75110A and SN75112 are characterized for operation from 0°C to 70°C.