SN74S374-ch, 2-input, 4.75-V to 5.25-V bipolar NAND gates | Gates and Inverters | 3 | Active | These devices contain four independent 2-input NAND buffer gates.
The SN5437, SN54LS37 and SN54S37 are characterized for operation over the full military range of -55°C to 125°C. The SN7437, SN74LS37 and SN74S37 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input NAND buffer gates.
The SN5437, SN54LS37 and SN54S37 are characterized for operation over the full military range of -55°C to 125°C. The SN7437, SN74LS37 and SN74S37 are characterized for operation from 0°C to 70°C. |
SN74S373Octal D-type Transparent Latches with 3-state Outputs | Integrated Circuits (ICs) | 3 | Active | These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off. |
SN74S374Octal D-Type Positive Edge Triggered Flip-Flops with 3-State Outputs | Flip Flops | 2 | Active | These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off. |
SN74S384-ch, 2-input, 4.75-V to 5.25-V bipolar NAND gates with open-collector outputs | Gates and Inverters | 4 | Active | These devices contain four independent 2-input NAND buffer gates with open-collector outputs. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate high VOHlevels.
The SN5438, SN54LS38, and SN54S38 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7438, SN74LS38, and SN74S38 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input NAND buffer gates with open-collector outputs. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate high VOHlevels.
The SN5438, SN54LS38, and SN54S38 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7438, SN74LS38, and SN74S38 are characterized for operation from 0°C to 70°C. |
SN74S51Dual 2-wide 2-input AND-OR-Invert Gates | Logic | 3 | Active | The '51 and 'S51 contain two independent 2-wide 2-input AND-OR-INVERT gates. They perform the Boolean function Y = AB + CD\.
The 'LS51 contains one 2-wide 3-input and one 2-wide 2-input AND-OR-INVERT gates. They perform the Boolean functions 1Y = (1A · 1B · 1C) + (1D · 1E · 1F)\ and 2Y = (2A · 2B) + (2C · 2D)\.
The SN5451, SN54LS51, and SN54S51 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7451, SN74LS51 and SN74S51 are characterized for operation from 0°C to 70°C.
The '51 and 'S51 contain two independent 2-wide 2-input AND-OR-INVERT gates. They perform the Boolean function Y = AB + CD\.
The 'LS51 contains one 2-wide 3-input and one 2-wide 2-input AND-OR-INVERT gates. They perform the Boolean functions 1Y = (1A · 1B · 1C) + (1D · 1E · 1F)\ and 2Y = (2A · 2B) + (2C · 2D)\.
The SN5451, SN54LS51, and SN54S51 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7451, SN74LS51 and SN74S51 are characterized for operation from 0°C to 70°C. |
| Logic | 2 | Active | These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B, and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the '85, 'LS85, and 'S85 are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data.
These four-bit magnitude comparators perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B, and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the '85, 'LS85, and 'S85 are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data. |
SN74SSQEA32882810-MHz, JEDEC SSTE32882 compliant 28-bit to 56-bit registered buffer with address-parity test | Specialty Logic | 1 | Active | This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDDof 1.5 V and on DDR3L registered DIMMs with VDDof 1.35 V.
All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn andYnand control net outputs DxCKEn,DxCSnand DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.
The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When theQCSENinput pin is open (or pulled high), the component has two chip select inputs,DCS0andDCS1, and two copies of each chip select output,QACS0,QACS1,QBCS0andQBCS1. This is the "QuadCS disabled" mode. When theQCSENinput pin is pulled low, the component has four chip select inputsDCS[3:0], and four chip select outputs,QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification,DCS[n:0]will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled.QxCS[n:0]will indicate all of the chip select outputs.
The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.
The SN74SSQEA32882 operates from a differential clock (CK andCK). Data are registered at the crossing of CK going HIGH, andCKgoing LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.
The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain outputERROUTLOW. The control signals (DCKE0, DCKE1, DODT0, DODT1,DCS[n:0]) are not part of this computation.
The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDDof 1.5 V and on DDR3L registered DIMMs with VDDof 1.35 V.
All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn andYnand control net outputs DxCKEn,DxCSnand DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.
The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When theQCSENinput pin is open (or pulled high), the component has two chip select inputs,DCS0andDCS1, and two copies of each chip select output,QACS0,QACS1,QBCS0andQBCS1. This is the "QuadCS disabled" mode. When theQCSENinput pin is pulled low, the component has four chip select inputsDCS[3:0], and four chip select outputs,QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification,DCS[n:0]will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled.QxCS[n:0]will indicate all of the chip select outputs.
The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.
The SN74SSQEA32882 operates from a differential clock (CK andCK). Data are registered at the crossing of CK going HIGH, andCKgoing LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers.
The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one clock cycle later. If they do not match the device pulls the open drain outputERROUTLOW. The control signals (DCKE0, DCKE1, DODT0, DODT1,DCS[n:0]) are not part of this computation.
The SN74SSQEA32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs. |
SN74SSTEB328661.5-V/1.8-V 25-bit configurable registered buffer with address-parity test | Integrated Circuits (ICs) | 1 | Active | This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meets SSTL_18 and SSTL_15 specifications (depending on Supply voltage level), except the open-drain error (QERR) output.
The SN74SSTEB32866 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low.
The SN74SSTEB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drainQERRpin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) andQERRsignals are generated.
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO andQERRsignals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTEB32866. TheQERRoutput of the first SN74SSTEB32866 is left floating, and the valid error information is latched on theQERRoutput of the second SN74SSTEB32866.
If an error occurs and theQERRoutput is driven low, it stays latched low for a minimum of two clock cycles or untilRESETis driven low. If two or more consecutive parity errors occur, theQERRoutput is driven low and latched low for a clock duration equal to the parity-error duration or untilRESETis driven low. The DIMM-dependent signals (DCKE,DCS, DODT, andCSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the SN74SSTEB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied,RESETmust be held in the low state during power up.
The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low, exceptQERR. The LVCMOSRESETand Cn inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCSandCSR) inputs and gates the Qn and PPO outputs from changing states when bothDCSandCSRinputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle afterDCSandCSRgo high), the device gates theQERRoutput from changing states. IfLPS1is low, theQERRoutput functions normally. TheRESETinput has priority over theDCSandCSRcontrol and, when driven low, forces the Qn and PPO outputs low and forces theQERRoutput high. If theDCScontrol functionality is not desired, theCSRinput can be hard-wired to ground, in which case the setup-time requirement forDCSis the same as for the other D data inputs. To control the low-power mode withDCSonly, theCSRinput should be pulled up to VCCthrough a pull-up resistor.
The two VREFpins (A3 and T3) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor.
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meets SSTL_18 and SSTL_15 specifications (depending on Supply voltage level), except the open-drain error (QERR) output.
The SN74SSTEB32866 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low.
The SN74SSTEB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drainQERRpin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) andQERRsignals are generated.
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO andQERRsignals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTEB32866. TheQERRoutput of the first SN74SSTEB32866 is left floating, and the valid error information is latched on theQERRoutput of the second SN74SSTEB32866.
If an error occurs and theQERRoutput is driven low, it stays latched low for a minimum of two clock cycles or untilRESETis driven low. If two or more consecutive parity errors occur, theQERRoutput is driven low and latched low for a clock duration equal to the parity-error duration or untilRESETis driven low. The DIMM-dependent signals (DCKE,DCS, DODT, andCSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the SN74SSTEB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied,RESETmust be held in the low state during power up.
The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low, exceptQERR. The LVCMOSRESETand Cn inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCSandCSR) inputs and gates the Qn and PPO outputs from changing states when bothDCSandCSRinputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle afterDCSandCSRgo high), the device gates theQERRoutput from changing states. IfLPS1is low, theQERRoutput functions normally. TheRESETinput has priority over theDCSandCSRcontrol and, when driven low, forces the Qn and PPO outputs low and forces theQERRoutput high. If theDCScontrol functionality is not desired, theCSRinput can be hard-wired to ground, in which case the setup-time requirement forDCSis the same as for the other D data inputs. To control the low-power mode withDCSonly, theCSRinput should be pulled up to VCCthrough a pull-up resistor.
The two VREFpins (A3 and T3) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor. |
SN74SSTU32864500-MHz, 25-bit configurable registered buffer with SSTL_18 inputs and outputs | Logic | 7 | Active | This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCCoperation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET)\ and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used.
The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ and Cn inputs always must be held at a valid logic high or low level.
The two VREFpins (A3 and T3), are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor.
The device also supports low-power active operation by monitoring both system chip select (DCS\ and CSR\) inputs and will gate the Qn outputs from changing states when both DCS\ and CSR\ inputs are high. If either DCS\ or CSR\ input is low, the Qn outputs function normally. The RESET\ input has priority over the DCS\ and CSR\ control and forces the output low. If the DCS\ control functionality is not desired, the CSR\ input can be hard-wired to ground, in which case, the setup-time requirement for DCS\ is the same as for the other D data inputs.
To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCCoperation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET)\ and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used.
The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ and Cn inputs always must be held at a valid logic high or low level.
The two VREFpins (A3 and T3), are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor.
The device also supports low-power active operation by monitoring both system chip select (DCS\ and CSR\) inputs and will gate the Qn outputs from changing states when both DCS\ and CSR\ inputs are high. If either DCS\ or CSR\ input is low, the Qn outputs function normally. The RESET\ input has priority over the DCS\ and CSR\ control and forces the output low. If the DCS\ control functionality is not desired, the CSR\ input can be hard-wired to ground, in which case, the setup-time requirement for DCS\ is the same as for the other D data inputs.
To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up. |
SN74SSTUB3286625-bit configurable registered buffer with address-parity test | Specialty Logic | 4 | Active | This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output.
The SN74SSTUB32866 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low.
The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drainQERRpin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) andQERRsignals are generated.
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO andQERRsignals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTUB32866. TheQERRoutput of the first SN74SSTUB32866 is left floating, and the valid error information is latched on theQERRoutput of the second SN74SSTUB32866.
If an error occurs and theQERRoutput is driven low, it stays latched low for a minimum of two clock cycles or untilRESETis driven low. If two or more consecutive parity errors occur, theQERRoutput is driven low and latched low for a clock duration equal to the parity-error duration or untilRESETis driven low. The DIMM-dependent signals (DCKE,DCS, DODT, andCSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the SN74SSTUB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied,RESETmust be held in the low state during power up.
The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low, exceptQERR. The LVCMOSRESETand Cn inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCSandCSR) inputs and gates the Qn and PPO outputs from changing states when bothDCSandCSRinputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle afterDCSandCSRgo high), the device gates theQERRoutput from changing states. IfLPS1is low, theQERRoutput functions normally. TheRESETinput has priority over theDCSandCSRcontrol and, when driven low, forces the Qn and PPO outputs low and forces theQERRoutput high. If theDCScontrol functionality is not desired, theCSRinput can be hard-wired to ground, in which case the setup-time requirement forDCSis the same as for the other D data inputs. To control the low-power mode withDCSonly, theCSRinput should be pulled up to VCCthrough a pullup resistor.
The two VREFpins (A3 and T3) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor.
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output.
The SN74SSTUB32866 operates from a differential clock (CLK andCLK). Data are registered at the crossing of CLK going high and CLK going low.
The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drainQERRpin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) andQERRsignals are generated.
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO andQERRsignals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTUB32866. TheQERRoutput of the first SN74SSTUB32866 is left floating, and the valid error information is latched on theQERRoutput of the second SN74SSTUB32866.
If an error occurs and theQERRoutput is driven low, it stays latched low for a minimum of two clock cycles or untilRESETis driven low. If two or more consecutive parity errors occur, theQERRoutput is driven low and latched low for a clock duration equal to the parity-error duration or untilRESETis driven low. The DIMM-dependent signals (DCKE,DCS, DODT, andCSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application,RESETis specified to be completely asynchronous with respect to CLK andCLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition ofRESETuntil the input receivers are fully enabled, the design of the SN74SSTUB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied,RESETmust be held in the low state during power up.
The device supports low-power standby operation. WhenRESETis low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, whenRESETis low, all registers are reset and all outputs are forced low, exceptQERR. The LVCMOSRESETand Cn inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCSandCSR) inputs and gates the Qn and PPO outputs from changing states when bothDCSandCSRinputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle afterDCSandCSRgo high), the device gates theQERRoutput from changing states. IfLPS1is low, theQERRoutput functions normally. TheRESETinput has priority over theDCSandCSRcontrol and, when driven low, forces the Qn and PPO outputs low and forces theQERRoutput high. If theDCScontrol functionality is not desired, theCSRinput can be hard-wired to ground, in which case the setup-time requirement forDCSis the same as for the other D data inputs. To control the low-power mode withDCSonly, theCSRinput should be pulled up to VCCthrough a pullup resistor.
The two VREFpins (A3 and T3) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREFpins to the external VREFpower supply. An unused VREFpin should be terminated with a VREFcoupling capacitor. |
