SN74LVC1G3208-EP Series

Enhanced Product Single 3-Input Positive OR-AND Gate

Catalog

Enhanced Product Single 3-Input Positive OR-AND Gate

Part	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Min]	Operating Temperature [Max]	Number of Circuits	Number of Inputs [custom]	Number of Inputs [custom]	Number of Inputs [custom]	Supplier Device Package	Mounting Type	Output Type	Logic Type	Package / Case	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Inputs
Texas Instruments 74LVC1G3208MDBVTEP	5.5 V	1.65 V	-55 °C	125 °C	1	3	2	1	SOT-23-6	Surface Mount	Single-Ended	AND/OR Gate	SOT-23-6	32 mA	32 mA
Texas Instruments SN74LVC1G3208DBVT	5.5 V	1.65 V	-40 °C	125 °C	1	3	2	1	SOT-23-6	Surface Mount	Single-Ended	AND/OR Gate	SOT-23-6	32 mA	32 mA
Texas Instruments V62/13605-01XE	5.5 V	1.65 V	-55 °C	125 °C	1				SOT-23-6	Surface Mount	Single-Ended	AND/OR Gate	SOT-23-6	32 mA	32 mA	3
Texas Instruments 74LVC1G3208DBVTG4	5.5 V	1.65 V	-40 °C	125 °C	1	3	2	1	SOT-23-6	Surface Mount	Single-Ended	AND/OR Gate	SOT-23-6	32 mA	32 mA
Texas Instruments SN74LVC1G3208YZTR	5.5 V	1.65 V	-40 °C	85 °C	1	3	2	1	6-DSBGA	Surface Mount	Single-Ended	AND/OR Gate	6-UFBGA DSBGA	32 mA	32 mA
Texas Instruments 74LVC1G3208DBVRG4	5.5 V	1.65 V	-40 °C	125 °C	1	3	2	1	SOT-23-6	Surface Mount	Single-Ended	AND/OR Gate	SOT-23-6	32 mA	32 mA
Texas Instruments SN74LVC1G3208YZPR	5.5 V	1.65 V	-40 °C	85 °C	1	3	2	1	6-DSBGA	Surface Mount	Single-Ended	AND/OR Gate	6-XFBGA DSBGA	32 mA	32 mA

Catalog

Enhanced Product Single 3-Input Positive OR-AND Gate

Key Features

• Available in the Texas Instruments NanoStar and NanoFree PackagesSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VProvides Down Translation to VCCMax tpdof 5 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VInput Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys= 250 mV Typ @ 3.3 V)Can Be Used in Three Combinations:OR-AND GateOR GateAND GateIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoStar and NanoFree PackagesSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VProvides Down Translation to VCCMax tpdof 5 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VInput Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys= 250 mV Typ @ 3.3 V)Can Be Used in Three Combinations:OR-AND GateOR GateAND GateIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ● C). NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ● C). NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.