SN74LVC138A-Q1 Series
Automotive Catalog 3-Line To 8-Line decoder/Demultiplexer
Manufacturer: Texas Instruments
Catalog
Automotive Catalog 3-Line To 8-Line decoder/Demultiplexer
Key Features
• ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)Operates From 2 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 5.8 ns at 3.3 VTypical VOLP(Output Ground Bounce)< 0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)> 2 V at VCC= 3.3 V, TA= 25°CSUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONSControlled BaselineOne Assembly/Test SiteOne Fabrication SiteAvailable in Military (–55°C/125°C) Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Custom temperature ranges availableESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)Operates From 2 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 5.8 ns at 3.3 VTypical VOLP(Output Ground Bounce)< 0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)> 2 V at VCC= 3.3 V, TA= 25°CSUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONSControlled BaselineOne Assembly/Test SiteOne Fabrication SiteAvailable in Military (–55°C/125°C) Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Custom temperature ranges available
Description
AI
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
