Texas Instruments

High Speed CMOS Logic 12-Stage Binary Counter

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels. The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times. In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

The SN74HC4066 device is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6V (peak) to be transmitted in either direction. Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. The SN74HC4066 device is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6V (peak) to be transmitted in either direction. Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

This eight-channel CMOS analog multiplexer/demultiplexer is terminal compatible with the function of the ’4051 device, and features injection-current effect control, which has excellent value in automotive applications where voltages in excess of normal supply voltages are common. The injection-current effect control allows signals at disabled analog input channels to exceed the supply voltage without affecting the signal of the enabled analog channel. This feature eliminates the need for external diode/resistor networks typically used to keep the analog channel signals within the supply-voltage range. This eight-channel CMOS analog multiplexer/demultiplexer is terminal compatible with the function of the ’4051 device, and features injection-current effect control, which has excellent value in automotive applications where voltages in excess of normal supply voltages are common. The injection-current effect control allows signals at disabled analog input channels to exceed the supply voltage without affecting the signal of the enabled analog channel. This feature eliminates the need for external diode/resistor networks typically used to keep the analog channel signals within the supply-voltage range.

This dual 4-to-1 CMOS analog multiplexer/demultiplexer is pin compatible with the 4052 function and also features injection-current effect control. This feature has excellent value in automotive applications where voltages in excess of normal supply voltages are common. The injection-current effect control allows signals at disabled analog input channels to exceed the supply voltage without affecting the signal of the enabled analog channel. This eliminates the need for external diode/resistor networks typically used to keep the analog channel signals within the supply voltage range. This dual 4-to-1 CMOS analog multiplexer/demultiplexer is pin compatible with the 4052 function and also features injection-current effect control. This feature has excellent value in automotive applications where voltages in excess of normal supply voltages are common. The injection-current effect control allows signals at disabled analog input channels to exceed the supply voltage without affecting the signal of the enabled analog channel. This eliminates the need for external diode/resistor networks typically used to keep the analog channel signals within the supply voltage range.

These octal buffers and line drivers feature the performance of the SNx4HC541 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. The 3-state outputs are controlled by a two-input NOR gate. If either output-enable (OE1orOE2) input is high, all eight outputs are in the high-impedance state. The SNx4HC541 devices provide true data at the outputs. These octal buffers and line drivers feature the performance of the SNx4HC541 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. The 3-state outputs are controlled by a two-input NOR gate. If either output-enable (OE1orOE2) input is high, all eight outputs are in the high-impedance state. The SNx4HC541 devices provide true data at the outputs.

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices. The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types. The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices. The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types.

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

High Speed CMOS Logic Octal Positive-Edge-Triggered D-Type Flip-Flops with 3-State Outputs

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage. CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage. CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.