Catalog
8-Bit Binary Counters With 3-State Output Registers
Key Features
• 2-V to 6-V VCCOperationHigh-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL LoadsLow Power Consumption, 80-µA Max ICCTypical tpd= 14 ns±6-mA Output Drive at 5 VLow Input Current of 1 µA Max8-Bit Counter With RegisterCounter Has Direct Clear2-V to 6-V VCCOperationHigh-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL LoadsLow Power Consumption, 80-µA Max ICCTypical tpd= 14 ns±6-mA Output Drive at 5 VLow Input Current of 1 µA Max8-Bit Counter With RegisterCounter Has Direct Clear
Description
AI
The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
