SN74HC541A Series

8-ch, 2-V to 6-V buffers with 3-state outputs

Catalog

8-ch, 2-V to 6-V buffers with 3-state outputs

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Logic Type	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Supplier Device Package	Number of Bits per Element	Number of Elements	Mounting Type	Package / Case [y]	Package / Case	Package / Case [x]	Package / Case [y]	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case
Texas Instruments CD74HC541PWR	2 V	6 V	Buffer Non-Inverting	125 °C	-55 °C	7.8 mA	7.8 mA	3-State	20-TSSOP	8	1	Surface Mount	4.4 mm	20-TSSOP	0.173 in
Texas Instruments SN74HC541DWR	2 V	6 V	Buffer Non-Inverting			7.8 mA	7.8 mA	3-State	20-SOIC	8	1	Surface Mount	0.295 in	20-SOIC		7.5 mm	85 °C	-40 °C
Texas Instruments CD74HC541EG4	2 V	6 V	Buffer Non-Inverting	125 °C	-55 °C	7.8 mA	7.8 mA	3-State	20-PDIP	8	1	Through Hole		20-DIP					7.62 mm	0.3 in
Texas Instruments CD74HC541E	2 V	6 V	Buffer Non-Inverting	125 °C	-55 °C	7.8 mA	7.8 mA	3-State	20-PDIP	8	1	Through Hole		20-DIP					7.62 mm	0.3 in
Texas Instruments SN74HC541NSR	2 V	6 V	Buffer Non-Inverting			7.8 mA	7.8 mA	3-State	20-SO	8	1	Surface Mount		20-SOIC			85 °C	-40 °C	5.3 mm	0.209 "
Texas Instruments CD74HC541M	2 V	6 V	Buffer Non-Inverting	125 °C	-55 °C	7.8 mA	7.8 mA	3-State	20-SOIC	8	1	Surface Mount	0.295 in	20-SOIC		7.5 mm
Texas Instruments SN74HC541NG4	2 V	6 V	Buffer Non-Inverting			7.8 mA	7.8 mA	3-State	20-PDIP	8	1	Through Hole		20-DIP			85 °C	-40 °C	7.62 mm	0.3 in
Texas Instruments SN74HC541DW	2 V	6 V	Buffer Non-Inverting			7.8 mA	7.8 mA	3-State	20-SOIC	8	1	Surface Mount	0.295 in	20-SOIC		7.5 mm	85 °C	-40 °C
Texas Instruments SN74HC541PWR	2 V	6 V	Buffer Non-Inverting			7.8 mA	7.8 mA	3-State	20-TSSOP	8	1	Surface Mount	4.4 mm	20-TSSOP	0.173 in		85 °C	-40 °C
Texas Instruments SN74HC541DWG4	2 V	6 V	Buffer Non-Inverting			7.8 mA	7.8 mA	3-State	20-SOIC	8	1	Surface Mount	0.295 in	20-SOIC		7.5 mm	85 °C	-40 °C

Catalog

8-ch, 2-V to 6-V buffers with 3-state outputs

Key Features

• ’HC540, CD74HCT540: inverting’HC541, ’HCT541: non-invertingBuffered inputsThree-state outputsBus line driving capabilityTypical propagation delay = 9 ns at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6 V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOH’HC540, CD74HCT540: inverting’HC541, ’HCT541: non-invertingBuffered inputsThree-state outputsBus line driving capabilityTypical propagation delay = 9 ns at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6 V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOH

Description

These octal buffers and line drivers feature the performance of the SNx4HC541 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. The 3-state outputs are controlled by a two-input NOR gate. If either output-enable (OE1orOE2) input is high, all eight outputs are in the high-impedance state. The SNx4HC541 devices provide true data at the outputs. These octal buffers and line drivers feature the performance of the SNx4HC541 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout. The 3-state outputs are controlled by a two-input NOR gate. If either output-enable (OE1orOE2) input is high, all eight outputs are in the high-impedance state. The SNx4HC541 devices provide true data at the outputs.