SN74HC193-Q1High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counter with Asynchronous Reset | Counters, Dividers | 10 | Active | The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD)\ input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD\ inputs.
These counters were designed to be cascaded without the need for external circuitry. The borrow (BO)\ output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)\ output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can be cascaded easily by feeding BO\ and CO\ to DOWN and UP, respectively, of the succeeding counter.
The ’HC193 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP or DOWN). The direction of counting is determined by which count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD)\ input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs.
A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and LOAD\ inputs.
These counters were designed to be cascaded without the need for external circuitry. The borrow (BO)\ output produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)\ output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can be cascaded easily by feeding BO\ and CO\ to DOWN and UP, respectively, of the succeeding counter. |
SN74HC202-ch, 4-input, 2-V to 6-V 5.2 mA drive strength NAND gate | Gates and Inverters | 13 | Active | This device contains two independent 4-input NAND gates. Each gate performs the Boolean function Y =A ● B ● C ● Din positive logic.
This device contains two independent 4-input NAND gates. Each gate performs the Boolean function Y =A ● B ● C ● Din positive logic. |
SN74HC212-ch, 4-input, 2-V to 6-V 5.2 mA drive strength AND gate | Logic | 13 | Active | This device contains two independent 4-input AND gates. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic.
This device contains two independent 4-input AND gates. Each gate performs the Boolean function Y = A ● B ● C ● D in positive logic. |
SN74HC2408-ch, 2-V to 6-V inverters with 3-state outputs | Integrated Circuits (ICs) | 15 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. |
SN74HC2418-ch, 2-V to 6-V buffers with 3-state outputs | Integrated Circuits (ICs) | 8 | Active | 8-ch, 2-V to 6-V buffers with 3-state outputs |
SN74HC244-EPEnhanced product 8-ch, 2-V to 6-V buffers with 3-state outputs | Integrated Circuits (ICs) | 24 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC244 are organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes noninverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC244 are organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes noninverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. |
SN74HC245AHigh Speed CMOS Logic Non-Inverting Octal-Bus Transceivers with 3-State Outputs | Integrated Circuits (ICs) | 14 | Active | These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. |
SN74HC251High Speed CMOS Logic 8-Input Multiplexer with 3-State Outputs | Signal Switches, Multiplexers, Decoders | 13 | Active | High Speed CMOS Logic 8-Input Multiplexer with 3-State Outputs |
SN74HC253-Q1Automotive Catalog Dual 4-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs | Signal Switches, Multiplexers, Decoders | 9 | Active | Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE)\ input. The outputs are disabled when their respective OE\ is high.
Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE)\ input. The outputs are disabled when their respective OE\ is high. |
SN74HC257High Speed CMOS Logic Quad 2-Input Multiplexers with Non-Inverting 3-State Outputs | Signal Switches, Multiplexers, Decoders | 12 | Active | The ’HC257 and ’HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE\) is active LOW. When OE\ is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions.
Moving data from two groups of registers to four common output buses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator.
The ’HC257 and ’HCT257 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select Input (S). The Output Enable input (OE\) is active LOW. When OE\ is HIGH, all of the outputs (1Y-4Y) are in the high impedance state regardless of all other input conditions.
Moving data from two groups of registers to four common output buses is a common use of the 257. The state of the Select input determines the particular register from which the data comes. It can also be used as a function generator. |
