Texas Instruments

These devices contain four independent 2-input OR gates. They perform the Boolean functions Y = A + B or Y = A\ \x95 B\ in positive logic. The SN54F32 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F32 is characterized for operation from 0°C to 70°C. These devices contain four independent 2-input OR gates. They perform the Boolean functions Y = A + B or Y = A\ \x95 B\ in positive logic. The SN54F32 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F32 is characterized for operation from 0°C to 70°C.

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ´F373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs will follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable () input can be used to place the eight outputs in either a normallogic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output-enable () input does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F373 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54F373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F373 is characterized for operation from 0°C to 70°C. These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ´F373 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs will follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable () input can be used to place the eight outputs in either a normallogic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output-enable () input does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F373 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54F373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F373 is characterized for operation from 0°C to 70°C.

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ´F374 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. A buffered output enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable () input does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F374 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54F374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F374 is characterized for operation from 0°C to 70°C. These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ´F374 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. A buffered output enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable () input does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F374 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54F374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F374 is characterized for operation from 0°C to 70°C.

The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The SN74F377A features a latched clock enable () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse ifis low. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at theinput. The SN74F377A is characterized for operation from 0°C to 70°C. The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The SN74F377A features a latched clock enable () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse ifis low. Clock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at theinput. The SN74F377A is characterized for operation from 0°C to 70°C.

These devices contain four independent 2-input NAND buffer gates with open-collector outputs. They perform the Boolean functionsor Y = A\ + B\ in positive logic. The open-collector outputs require pullup resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. The SN54F38 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F38 is characterized for operation from 0°C to 70°C. These devices contain four independent 2-input NAND buffer gates with open-collector outputs. They perform the Boolean functionsor Y = A\ + B\ in positive logic. The open-collector outputs require pullup resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. The SN54F38 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F38 is characterized for operation from 0°C to 70°C.

These identity comparators perform comparisons on two 8-bit binary or BCD words. They provideoutputs. The SN54F521 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F521 is characterized for operation from 0°C to 70°C. These identity comparators perform comparisons on two 8-bit binary or BCD words. They provideoutputs. The SN54F521 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F521 is characterized for operation from 0°C to 70°C.

The ´F541 octal buffer/line driver is ideal for driving bus lines or buffering memory address registers. The device features inputs and outputs on opposite sides of the package to facilitate printed-circuit-board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output enable (or) input is high, all eight outputs are in the high-impedance state. The SN54F541 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F251 is characterized for operation from 0°C to 70°C. The ´F541 octal buffer/line driver is ideal for driving bus lines or buffering memory address registers. The device features inputs and outputs on opposite sides of the package to facilitate printed-circuit-board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output enable (or) input is high, all eight outputs are in the high-impedance state. The SN54F541 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F251 is characterized for operation from 0°C to 70°C.

The SN74F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output enable (or) inputs are provided for each register to permit independent control in either direction of data flow. The A outputs are characterized to sink 24 mA while the B outputs are characterized to sink 64 mA. The A-to-B enable () input must be low in order to enter data from A or to output data from B. Havinglow andlow makes the A-to-B latches transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the,, andinputs. The SN74F543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN74F543 is characterized for operation from 0°C to 70°C. A-to-B data flow is shown; B-to-A flow control is the same except that it uses,, and. Output level before the indicated steady-state input conditions were established. The SN74F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output enable (or) inputs are provided for each register to permit independent control in either direction of data flow. The A outputs are characterized to sink 24 mA while the B outputs are characterized to sink 64 mA. The A-to-B enable () input must be low in order to enter data from A or to output data from B. Havinglow andlow makes the A-to-B latches transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the,, andinputs. The SN74F543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN74F543 is characterized for operation from 0°C to 70°C. A-to-B data flow is shown; B-to-A flow control is the same except that it uses,, and. Output level before the indicated steady-state input conditions were established.

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ´F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enableinput does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54F573 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F573 is characterized for operation from 0°C to 70°C. These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ´F573 are transparent D-type latches. While the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enableinput does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54F573 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F573 is characterized for operation from 0°C to 70°C.

This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs. A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enabledoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F574 is characterized for operation from 0°C to 70°C. This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs. A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enabledoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F574 is characterized for operation from 0°C to 70°C.