
SN74F574 Series
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Manufacturer: Texas Instruments
Catalog
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs
Key Features
• Eight D-Type Flip-Flops in a Single Package3-State Bus-Driving True OutputsFull Parallel Access for LoadingBuffered Control InputsPackage Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPsEight D-Type Flip-Flops in a Single Package3-State Bus-Driving True OutputsFull Parallel Access for LoadingBuffered Control InputsPackage Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
Description
AI
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.
A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output enabledoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN74F574 is characterized for operation from 0°C to 70°C.
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.
A buffered output enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output enabledoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN74F574 is characterized for operation from 0°C to 70°C.