SN74F157AQuadruple 2-Line To 1-Line Data Selectors/Multiplexers | Logic | 5 | Active | The ´F157A is a quadruple 2-input data selector/multiplexer featuring a common strobe (G\) input. When the strobe is high, all outputs are low. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The ´F157A provides true data.
The SN54F157A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F157A is characterized for operation from 0°C to 70°C.
The ´F157A is a quadruple 2-input data selector/multiplexer featuring a common strobe (G\) input. When the strobe is high, all outputs are low. When the strobe is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The ´F157A provides true data.
The SN54F157A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F157A is characterized for operation from 0°C to 70°C. |
| Counters, Dividers | 2 | Active | This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is asynchronous, and a low logic level at the clear (CLR\) input sets all four of the flip-flop outputs to low, regardless of the levels of CLK, LOAD\, ENP, and ENT.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD\ that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.
This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is asynchronous, and a low logic level at the clear (CLR\) input sets all four of the flip-flop outputs to low, regardless of the levels of CLK, LOAD\, ENP, and ENT.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD\ that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times. |
| Counters, Dividers | 3 | Active | This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is synchronous, and a low logic level at the clear (CLR\) input sets all four of the flip-flop outputs to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD\ that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.
This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is synchronous, and a low logic level at the clear (CLR\) input sets all four of the flip-flop outputs to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD\ that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times. |
| Logic | 3 | Obsolete | This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0°C to 70°C.
This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0°C to 70°C. |
SN74F175Quadruple D-Type Flip-Flops With Clear | Flip Flops | 4 | Active | This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear (CLR)\ input. Information at the data (D) inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. |
SN74F202-ch, 4-input, 4.5-V to 5.5-V bipolar NAND gates | Gates and Inverters | 6 | Active | These devices contain two independent 4-input NAND gates. They perform the Boolean functionsorin positive logic.
The SN54F20 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F20 is characterized for operation from 0°C to 70°C.
These devices contain two independent 4-input NAND gates. They perform the Boolean functionsorin positive logic.
The SN54F20 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F20 is characterized for operation from 0°C to 70°C. |
SN74F212-ch, 4-input, 4.5-V to 5.5-V high-speed (6 ns) bipolar AND gate | Integrated Circuits (ICs) | 2 | Obsolete | These devices contain two independent 4-input AND gates. They perform the Boolean functions Y = A \x95 B \x95 C \x95 D orin positive logic.
The SN54F21 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F21 is characterized for operation from 0°C to 70°C.
These devices contain two independent 4-input AND gates. They perform the Boolean functions Y = A \x95 B \x95 C \x95 D orin positive logic.
The SN54F21 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F21 is characterized for operation from 0°C to 70°C. |
SN74F2408-ch, 4.5-V to 5.5-V bipolar inverters with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the ´F241 and ´F244, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical(active-low output-enable) inputs, and complementary OE andinputs.
The ´F240 is organized as two 4-bit buffers/line drivers with separate output enable () inputs. Whenis low, the device passes data from the A inputs to the Y outputs. Whenis high, the outputs are in the high-impedance state.
The SN74F240 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F240 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F240 is characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the ´F241 and ´F244, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical(active-low output-enable) inputs, and complementary OE andinputs.
The ´F240 is organized as two 4-bit buffers/line drivers with separate output enable () inputs. Whenis low, the device passes data from the A inputs to the Y outputs. Whenis high, the outputs are in the high-impedance state.
The SN74F240 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F240 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F240 is characterized for operation from 0°C to 70°C. |
SN74F2418-ch, 4.5-V to 5.5-V bipolar buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the ´F240 and ´F244, these devices provide the choice of selected combinations of inverting and non inverting outputs, symmetrical(active-low output-enable) inputs, and complementary OE andinputs.
The SN54F241 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F241 is characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the ´F240 and ´F244, these devices provide the choice of selected combinations of inverting and non inverting outputs, symmetrical(active-low output-enable) inputs, and complementary OE andinputs.
The SN54F241 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F241 is characterized for operation from 0°C to 70°C. |
SN74F2448-ch, 4.5-V to 5.5-V bipolar buffers with 3-state outputs | Logic | 7 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the ´F240 and ´F241, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical(active-low output-enable) inputs, and complementary OE andinputs.
The ´F244 is organized as two 4-bit buffers/line drivers with separate output enable () inputs. Whenis low, the device passes data from the A inputs to the Y outputs. Whenis high, the outputs are in the high-impedance state.
The SN74F244 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F244 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F244 is characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the ´F240 and ´F241, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical(active-low output-enable) inputs, and complementary OE andinputs.
The ´F244 is organized as two 4-bit buffers/line drivers with separate output enable () inputs. Whenis low, the device passes data from the A inputs to the Y outputs. Whenis high, the outputs are in the high-impedance state.
The SN74F244 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54F244 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F244 is characterized for operation from 0°C to 70°C. |
