SN74ALVTH16282720-ch, 2.3-V to 3.6-V buffers with bus-hold, TTL-compatible CMOS inputs and 3-state outputs | Logic | 3 | Obsolete | The 'ALVTH162827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
All outputs are designed to sink up to 12 mA, and include equivalent 30-resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH162827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH162827 is characterized for operation from -40°C to 85°C.
The 'ALVTH162827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
All outputs are designed to sink up to 12 mA, and include equivalent 30-resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH162827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH162827 is characterized for operation from -40°C to 85°C. |
SN74ALVTH163732.5-V/3.3-V 16-Bit Transparent D-Type Latches With 3-State Outputs | Integrated Circuits (ICs) | 5 | Obsolete | The 'ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16373 is characterized for operation from -40°C to 85°C.
The 'ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16373 is characterized for operation from -40°C to 85°C. |
SN74ALVTH163742.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs | Logic | 6 | Obsolete | The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OEdoes not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.
The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.
The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OEdoes not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.
The SN74ALVTH16374 is characterized for operation from -40°C to 85°C. |
SN74ALVTH166012.5-V/3.3-V 18-bit universal bus transceiver with 3-state outputs | Logic | 3 | Obsolete | The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C.
The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16601 is characterized for operation from -40°C to 85°C. |
SN74ALVTH168212.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs | Flip Flops | 3 | Obsolete | The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C.
The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.
A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C. |
SN74ALVTH1682720-ch, 2.3-V to 3.6-V buffers with bus-hold, TTL-compatible CMOS inputs and 3-state outputs | Integrated Circuits (ICs) | 3 | Obsolete | The 'ALVTH16827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16827 is characterized for operation from -40°C to 85°C.
The 'ALVTH16827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16827 is characterized for operation from -40°C to 85°C. |
| Buffers, Drivers, Receivers, Transceivers | 5 | Obsolete | The ’ALVTHR16245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated.
All outputs are designed to sink up to 12 mA, and include equivalent 30-resistors to reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The ’ALVTHR16245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated.
All outputs are designed to sink up to 12 mA, and include equivalent 30-resistors to reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74AS004-ch, 2-input, 4.5-V to 5.5-V bipolar NAND gates | Gates and Inverters | 3 | Active | These devices contain four independent 2-input positive-NAND gates. They perform the Boolean functionsor Y = A\ + B\ in positive logic.
The SN54ALS00A and SN54AS00 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS00A and SN74AS00 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input positive-NAND gates. They perform the Boolean functionsor Y = A\ + B\ in positive logic.
The SN54ALS00A and SN54AS00 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS00A and SN74AS00 are characterized for operation from 0°C to 70°C. |
SN74AS024-ch, 2-input, 4.5-V to 5.5-V bipolar NOR gates | Gates and Inverters | 4 | Active | These devices contain four independent 2-input positive-NOR gates. They perform the Boolean functionsor Y = A\ \x95 B\ in positive logic.
The SN54ALS02A and SN54AS02 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS02A and SN74AS02 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input positive-NOR gates. They perform the Boolean functionsor Y = A\ \x95 B\ in positive logic.
The SN54ALS02A and SN54AS02 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS02A and SN74AS02 are characterized for operation from 0°C to 70°C. |
SN74AS046-ch, 4.5-V to 5.5-V bipolar inverters | Gates and Inverters - Multi-Function, Configurable | 4 | Active | These devices contain six independent hex inverters. They perform the Boolean function Y = A\.
The SN54ALS04B and SN54AS04 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS04B and SN74AS04 are characterized for operation from 0°C to 70°C.
These devices contain six independent hex inverters. They perform the Boolean function Y = A\.
The SN54ALS04B and SN54AS04 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS04B and SN74AS04 are characterized for operation from 0°C to 70°C. |
