SN74ALVTH16374 Series

2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Catalog

2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Part	Function	Type	Supplier Device Package	Number of Bits per Element	Current - Quiescent (Iq)	Input Capacitance	Clock Frequency	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Package / Case	Package / Case [custom]	Trigger Type	Max Propagation Delay @ V, Max CL	Number of Elements	Output Type	Package / Case [y]	Package / Case [y]
Texas Instruments SN74ALVTH16374GR	Standard	D-Type	48-TSSOP	8	100 µA	3.5 pF	250 MHz	24 mA	32 mA	64 mA	8 mA	Surface Mount	85 °C	-40 °C	2.7 V 3.6 V	2.3 V 3 V	48-TFSOP	0.24 in	6.1 mm	Positive Edge	3.2 ns	2	Non-Inverted Tri-State
Texas Instruments SN74ALVTH16374KR	Standard	D-Type	56-BGA Microstar Junior (7x4.5)	8	100 µA	3.5 pF	250 MHz	24 mA	32 mA	64 mA	8 mA	Surface Mount	85 °C	-40 °C	2.7 V 3.6 V	2.3 V 3 V	56-VFBGA			Positive Edge	3.2 ns	2	Non-Inverted Tri-State
Texas Instruments SN74ALVTH16374DL	Standard	D-Type	48-SSOP	8	100 µA	3.5 pF	250 MHz	8 mA			8 mA	Surface Mount	85 °C	-40 °C	2.7 V 3.6 V	2.3 V 3 V	48-BSSOP			Positive Edge	3.2 ns	2	Non-Inverted Tri-State	0.295 in	7.5 mm
Texas Instruments SN74ALVTH16374DLR	Standard	D-Type	48-SSOP	8	100 µA	3.5 pF	250 MHz	24 mA	32 mA	64 mA	8 mA	Surface Mount	85 °C	-40 °C	2.7 V 3.6 V	2.3 V 3 V	48-BSSOP			Positive Edge	3.2 ns	2	Non-Inverted Tri-State	0.295 in	7.5 mm
Texas Instruments 74ALVTH16374ZQLR	Standard	D-Type	56-BGA Microstar Junior (7x4.5)	8	100 µA	3.5 pF	250 MHz	24 mA	32 mA	64 mA	8 mA	Surface Mount	85 °C	-40 °C	2.7 V 3.6 V	2.3 V 3 V	56-VFBGA			Positive Edge	3.2 ns	2	Non-Inverted Tri-State
Texas Instruments SN74ALVTH16374VR	Standard	D-Type		8	100 µA	3.5 pF	250 MHz	24 mA	32 mA	64 mA	8 mA	Surface Mount	85 °C	-40 °C	2.7 V 3.6 V	2.3 V 3 V	48-TFSOP	0.173 in 4.4 mm		Positive Edge	3.2 ns	2	Non-Inverted Tri-State

Catalog

2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Key Features

• State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CHigh Drive (-24/24 mA at 2.5-V VCCand -32/64 mA at 3.3-V )Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD ProtectionExceeds 2000 V Per MIL-STD-883, Method 3015Exceeds 200 V Using Machine ModelExceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments.State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CHigh Drive (-24/24 mA at 2.5-V VCCand -32/64 mA at 3.3-V )Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD ProtectionExceeds 2000 V Per MIL-STD-883, Method 3015Exceeds 200 V Using Machine ModelExceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments.

Description

The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OEdoes not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16374 is characterized for operation from -40°C to 85°C. The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OEdoes not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.