SN74ALVTH16821 Series

2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs

Catalog

2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Current - Quiescent (Iq)	Number of Elements	Clock Frequency	Max Propagation Delay @ V, Max CL	Number of Bits per Element	Input Capacitance	Package / Case	Package / Case	Package / Case [y]	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Output Type	Mounting Type	Type	Function	Supplier Device Package	Trigger Type	Package / Case	Package / Case
Texas Instruments SN74ALVTH16821VR	85 °C	-40 °C	100 µA	2	150 MHz	3.5 ns	10	3.5 pF	0.173 in	56-TFSOP	4.4 mm	2.7 V 3.6 V	2.3 V 3 V	24 mA	32 mA	64 mA	8 mA	Non-Inverted Tri-State	Surface Mount	D-Type	Standard	56-TVSOP	Positive Edge
Texas Instruments SN74ALVTH16821DLR	85 °C	-40 °C	100 µA	2	150 MHz	3.5 ns	10	3.5 pF		56-BSSOP		2.7 V 3.6 V	2.3 V 3 V	24 mA	32 mA	64 mA	8 mA	Non-Inverted Tri-State	Surface Mount	D-Type	Standard	56-SSOP	Positive Edge	0.295 in	7.5 mm
Texas Instruments SN74ALVTH16821DL	85 °C	-40 °C	100 µA	2	150 MHz	3.5 ns	10	3.5 pF		56-BSSOP		2.7 V 3.6 V	2.3 V 3 V	24 mA	32 mA	64 mA	8 mA	Non-Inverted Tri-State	Surface Mount	D-Type	Standard	56-SSOP	Positive Edge	0.295 in	7.5 mm

Catalog

2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs

Key Features

• State-of-the-Art Advanced BiCMOS Technology (ABT)WidebusTMDesign for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 3.3 V, TA= 25°CHigh-Drive (-24/24 mA at 2.5-V and-32/64 mA at 3.3-V VCC)Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments Incorporated.State-of-the-Art Advanced BiCMOS Technology (ABT)WidebusTMDesign for 2.5-V and 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)Typical VOLP(Output Ground Bounce) < 0.8 V at VCC= 3.3 V, TA= 25°CHigh-Drive (-24/24 mA at 2.5-V and-32/64 mA at 3.3-V VCC)Power Off Disables Outputs, Permitting Live InsertionHigh-Impedance State During Power Up and Power Down Prevents Driver ConflictUses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From FloatingAuto3-State Eliminates Bus Current Loading When Output Exceeds VCC+ 0.5 VLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic MethodFlow-Through Architecture Facilitates Printed Circuit Board LayoutDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoisePackage Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) PackageWidebus is a trademark of Texas Instruments Incorporated.

Description

The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs. A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C. The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs. A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCCis between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C.