| Integrated Circuits (ICs) | 1 | Active | These data selectors/multiplexers provide full binary decoding to select one-of-eight data sources. The strobe (G\) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low.
The SN54ALS151 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS151 and SN74AS151 are characterized for operation from 0°C to 70°C.
These data selectors/multiplexers provide full binary decoding to select one-of-eight data sources. The strobe (G\) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low.
The SN54ALS151 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS151 and SN74AS151 are characterized for operation from 0°C to 70°C. |
SN74AS153Dual 1-of-4 Data Selectors/Multiplexers | Logic | 2 | Active | These dual 1-of-4 data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections.
The SN54ALS153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS153 and SN74AS153 are characterized for operation from 0°C to 70°C.
These dual 1-of-4 data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections.
The SN54ALS153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS153 and SN74AS153 are characterized for operation from 0°C to 70°C. |
SN74AS157Quadruple 1-of-2 Data Selectors/Multiplexers | Integrated Circuits (ICs) | 4 | Active | These data selectors/multiplexers contain inverters and drivers to supply full data selection to the four output gates. A separate strobe (G\) input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The ´ALS157A and SN74AS157 present true data. The ´ALS158 and SN74AS158 present inverted data to minimize propagation delay time.
The SN54ALS157A and SN54ALS158 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS157A, SN74ALS158, SN74AS157, and SN74AS158 are characterized for operation from 0°C to 70°C.
These data selectors/multiplexers contain inverters and drivers to supply full data selection to the four output gates. A separate strobe (G\) input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The ´ALS157A and SN74AS157 present true data. The ´ALS158 and SN74AS158 present inverted data to minimize propagation delay time.
The SN54ALS157A and SN54ALS158 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS157A, SN74ALS158, SN74AS157, and SN74AS158 are characterized for operation from 0°C to 70°C. |
SN74AS158Quadruple 1-of-2 Data Selectors/Multiplexers | Gates and Inverters | 3 | Active | These data selectors/multiplexers contain inverters and drivers to supply full data selection to the four output gates. A separate strobe (G\) input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The ´ALS157A and SN74AS157 present true data. The ´ALS158 and SN74AS158 present inverted data to minimize propagation delay time.
The SN54ALS157A and SN54ALS158 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS157A, SN74ALS158, SN74AS157, and SN74AS158 are characterized for operation from 0°C to 70°C.
These data selectors/multiplexers contain inverters and drivers to supply full data selection to the four output gates. A separate strobe (G\) input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. The ´ALS157A and SN74AS157 present true data. The ´ALS158 and SN74AS158 present inverted data to minimize propagation delay time.
The SN54ALS157A and SN54ALS158 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS157A, SN74ALS158, SN74AS157, and SN74AS158 are characterized for operation from 0°C to 70°C. |
| Integrated Circuits (ICs) | 4 | Active | These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The \x92ALS161B, \x92ALS163B, \x92AS161, and \x92AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the \x92ALS161B and \x92AS161 devices is asynchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD\, or enable inputs. The clear function for the SN54ALS162B, \x92ALS163B, and \x92AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with QAhigh). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The \x92ALS161B, \x92ALS163B, \x92AS161, and \x92AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the \x92ALS161B and \x92AS161 devices is asynchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD\, or enable inputs. The clear function for the SN54ALS162B, \x92ALS163B, and \x92AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with QAhigh). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C. |
| Counters, Dividers | 3 | Active | These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The \x92ALS161B, \x92ALS163B, \x92AS161, and \x92AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the \x92ALS161B and \x92AS161 devices is asynchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD\, or enable inputs. The clear function for the SN54ALS162B, \x92ALS163B, and \x92AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with QAhigh). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The \x92ALS161B, \x92ALS163B, \x92AS161, and \x92AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform.
These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD\) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the \x92ALS161B and \x92AS161 devices is asynchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD\, or enable inputs. The clear function for the SN54ALS162B, \x92ALS163B, and \x92AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a high-level pulse while the count is maximum (9 or 15, with QAhigh). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C. |
SN74AS174Hex D-Type Positive-Edge-Triggered Flip-Flops With Clear | Integrated Circuits (ICs) | 4 | Active | These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits. |
SN74AS175BQuadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear | Flip Flops | 4 | Active | These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits. |
SN74AS1944-Bit Bidirectional Universal Shift Registers | Shift Registers | 3 | Active | These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:
Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.
These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operating-mode-control (S0, S1) inputs, and a direct overriding clear (CLR\) line. The registers have four distinct modes of operation:
Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C. |
SN74AS202-ch, 4-input, 4.5-V to 5.5-V bipolar NAND gates | Gates and Inverters | 5 | Active | These devices contain two independent 4-input positive-NAND gates. They perform the Boolean functionsor\ in positive logic.
The SN54ALS20A and SN54AS20 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS20A and SN74AS20 are characterized for operation from 0°C to 70°C.
These devices contain two independent 4-input positive-NAND gates. They perform the Boolean functionsor\ in positive logic.
The SN54ALS20A and SN54AS20 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS20A and SN74AS20 are characterized for operation from 0°C to 70°C. |
