Texas Instruments

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Dual 2-Line To 4-Line Decoders/Demultiplexers

This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic.

The SNx4HC148 is an 8-input priority encoder. Added input enable (EI) and output enable (EO) signals allow for cascading multiple stages without added external circuitry. The SNx4HC148 is an 8-input priority encoder. Added input enable (EI) and output enable (EO) signals allow for cascading multiple stages without added external circuitry.

Dual 4-Line To 1-Line Data Selectors/Multiplexers

The SNx4HC157 contains four data selectors/multiplexers to select one of two data sources. All channels are controlled by the same address select (A/B) input, and strobe (G) input. A high level at the strobe terminal forces all outputs low. The SNx4HC157 contains four data selectors/multiplexers to select one of two data sources. All channels are controlled by the same address select (A/B) input, and strobe (G) input. A high level at the strobe terminal forces all outputs low.

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LDis held high. While SH/LDis low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LDis held high. While SH/LDis low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

Parallel-Load 8-Bit Shift Registers

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.