Texas Instruments

The ´ALS857 are hextuple 2-line to 1-line multiplexers with 3-state outputs. The devices can provide either true (COMP low) or inverted (COMP high) data at the Y outputs. In addition, the ´ALS857 perform the logical AND function (A \x95 B) and the clear function as well. The four modes of operation are: In either of the first two modes, OPER = 0 is high if all the selected A or B inputs are low. The six Y outputs and the OPER = 0 output are all 3-state and rated at 12-mA and 24-mA IOLfor the SN54ALS857 and SN74ALS857, respectively. All outputs can be placed in the high-impedance state by applying a high level to the COMP, S0, and S1 inputs simultaneously. The SN54ALS857 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS857 is characterized for operation from 0°C to 70°C. The ´ALS857 are hextuple 2-line to 1-line multiplexers with 3-state outputs. The devices can provide either true (COMP low) or inverted (COMP high) data at the Y outputs. In addition, the ´ALS857 perform the logical AND function (A \x95 B) and the clear function as well. The four modes of operation are: In either of the first two modes, OPER = 0 is high if all the selected A or B inputs are low. The six Y outputs and the OPER = 0 output are all 3-state and rated at 12-mA and 24-mA IOLfor the SN54ALS857 and SN74ALS857, respectively. All outputs can be placed in the high-impedance state by applying a high level to the COMP, S0, and S1 inputs simultaneously. The SN54ALS857 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS857 is characterized for operation from 0°C to 70°C.

These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear () input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable () input is at a high logic level. The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C. These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear () input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable () input is at a high logic level. The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C.

These devices contain four independent 2-input positive-AND gates. They perform the Boolean functions Y = A \x95 B orin positive logic. The SN54ALS08 and SN54AS08 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS08 and SN74AS08 are characterized for operation from 0°C to 70°C. These devices contain four independent 2-input positive-AND gates. They perform the Boolean functions Y = A \x95 B orin positive logic. The SN54ALS08 and SN54AS08 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS08 and SN74AS08 are characterized for operation from 0°C to 70°C.

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.

These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers. Output-enable () and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data whenis low. In the isolation mode (high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended maximum IOLin the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646, SN54ALS648, or SN74ALS648A. The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are characterized for operation from 0°C to 70°C. These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers. Output-enable () and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data whenis low. In the isolation mode (high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended maximum IOLin the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646, SN54ALS648, or SN74ALS648A. The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are characterized for operation from 0°C to 70°C.

These devices contain six independent 2-input NOR drivers. They perform the Boolean functionsor Y = A\ \x95 B\ in positive logic. The SN54ALS805A and SN54AS805B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS805A and SN74AS805B are characterized for operation from 0°C to 70°C. These devices contain six independent 2-input NOR drivers. They perform the Boolean functionsor Y = A\ \x95 B\ in positive logic. The SN54ALS805A and SN54AS805B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS805A and SN74AS805B are characterized for operation from 0°C to 70°C.

These devices contain six independent 2-input AND drivers. They perform the Boolean functions Y = A \x95 B orin positive logic. The SN54AS808B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS808B is characterized for operation from 0°C to 70°C. These devices contain six independent 2-input AND drivers. They perform the Boolean functions Y = A \x95 B orin positive logic. The SN54AS808B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS808B is characterized for operation from 0°C to 70°C.

These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers. With the clock-enable () input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Takinghigh disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has inverting (D\) inputs. Taking the clear () input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable () input can be used to place the nine outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS823A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS823A and SN74AS824A are characterized for operation from 0°C to 70°C. These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers. With the clock-enable () input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Takinghigh disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has inverting (D\) inputs. Taking the clear () input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable () input can be used to place the nine outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS823A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS823A and SN74AS824A are characterized for operation from 0°C to 70°C.

The ´BCT126A bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. The SN54BCT126A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT126A is characterized for operation from 0°C to 70°C. The ´BCT126A bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. The SN54BCT126A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT126A is characterized for operation from 0°C to 70°C.

These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated. These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated.