Catalog
Parallel-Load 8-Bit Shift Registers
Key Features
• Wide Operating Voltage Range of 2 V to 6 VOutputs Can Drive Up to 10 LSTTL LoadsLow Power Consumption, 80-µA Maximum ICCTypical tpd= 13 ns±4-mA Output Drive at 5 VLow Input Current of 1 µA MaximumComplementary OutputsDirect Overriding Load (Data) InputsGated Clock InputsParallel-to-Serial Data ConversionOn Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily Include Testingof All Parameters.Wide Operating Voltage Range of 2 V to 6 VOutputs Can Drive Up to 10 LSTTL LoadsLow Power Consumption, 80-µA Maximum ICCTypical tpd= 13 ns±4-mA Output Drive at 5 VLow Input Current of 1 µA MaximumComplementary OutputsDirect Overriding Load (Data) InputsGated Clock InputsParallel-to-Serial Data ConversionOn Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily Include Testingof All Parameters.
Description
AI
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LDis held high. While SH/LDis low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LDis held high. While SH/LDis low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
