SN54HC175Quadruple D-type Flip-Flops With Clear | Logic | 4 | Active | These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementary outputs from each flip-flop.
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. The ’HC175 devices feature complementary outputs from each flip-flop. |
| Integrated Circuits (ICs) | 1 | Active | These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. |
SN54HC251Data Selectors/Multiplexers With 3-State Outputs | Integrated Circuits (ICs) | 1 | Active | Data Selectors/Multiplexers With 3-State Outputs |
SN54HC257Quad 2-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs | Signal Switches, Multiplexers, Decoders | 1 | Active | These devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (G\) input is at a high logic level.
To ensure the high-impedance state during power up or power down, (G\) should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (G\) input is at a high logic level.
To ensure the high-impedance state during power up or power down, (G\) should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Latches | 2 | Active | 8-Bit Addressable Latches |
| Flip Flops | 6 | Active | The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
The SNx4HC273 devices are positive-edge-triggered D-type flip-flops with a direct active low clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. |
| Logic | 1 | Active | Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. |
SN54HC365Military 6-ch, 2-V to 6-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 1 | Active | Military 6-ch, 2-V to 6-V buffers with 3-state outputs |
SN54HC373Octal D-type Transparent Latches With 3-State Outputs | Logic | 3 | Active | These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’HC373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. |
| Integrated Circuits (ICs) | 2 | Active | This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the SN54HC373-DIE are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.
This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the SN54HC373-DIE are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. |
