| Development Boards, Kits, Programmers | 6 | Obsolete | |
ADC108S0228-Channel, 50 ksps to 200 ksps, 10-Bit A/D Converter | Data Acquisition | 2 | Active | The ADC108S022 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 50 ksps to 200 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC108S022 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 1.1 mW and 6.4 mW, respectively. The power-down feature reduces the power consumption to 0.09 µW using a +3V supply and 0.3 µW using a +5V supply.
The ADC108S022 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40°C to +105°C is ensured.
The ADC108S022 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 50 ksps to 200 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC108S022 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 1.1 mW and 6.4 mW, respectively. The power-down feature reduces the power consumption to 0.09 µW using a +3V supply and 0.3 µW using a +5V supply.
The ADC108S022 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40°C to +105°C is ensured. |
ADC108S0528-Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter | Integrated Circuits (ICs) | 1 | Active | The ADC108S052 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 200 ksps to 500 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC108S052 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 1.5 mW and 7.5 mW, respectively. The power-down feature reduces the power consumption to 0.09 µW using a +3V supply and 0.30 µW using a +5V supply.
The ADC108S052 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40°C to +105°C is ensured.
The ADC108S052 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 200 ksps to 500 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC108S052 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 1.5 mW and 7.5 mW, respectively. The power-down feature reduces the power consumption to 0.09 µW using a +3V supply and 0.30 µW using a +5V supply.
The ADC108S052 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40°C to +105°C is ensured. |
ADC108S1028-Channel, 500 kSPS to 1 MSPS, 10-Bit A/D Converter | Data Acquisition | 2 | Active | The ADC108S102 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 500 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC108S102 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 2.1 mW and 9.4 mW, respectively. The power-down feature reduces the power consumption to 0.09 µW using a +3V supply and 0.30 µW using a +5V supply.
The ADC108S102 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40°C to +105°C is ensured.
The ADC108S102 is a low-power, eight-channel CMOS 10-bit analog-to-digital converter specified for conversion throughput rates of 500 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.
The ADC108S102 may be operated with independent analog and digital supplies. The analog supply (VA) can range from +2.7V to +5.25V, and the digital supply (VD) can range from +2.7V to VA. Normal power consumption using a +3V or +5V supply is 2.1 mW and 9.4 mW, respectively. The power-down feature reduces the power consumption to 0.09 µW using a +3V supply and 0.30 µW using a +5V supply.
The ADC108S102 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40°C to +105°C is ensured. |
| Integrated Circuits (ICs) | 5 | Obsolete | |
ADC10D020Dual-Channel, 10-Bit, 20-MSPS Analog-to-Digital Converter (ADC) | Data Acquisition | 1 | Active | The ADC10D020 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 MSPS while consuming a typical 150 mW from a single 3.0V supply. No missing codes is ensured over the full operating temperature range. The unique two stage architecture achieves 9.5 Effective Bits over the entire Nyquist band at 20 MHz sample rate. An output formatting choice of offset binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error.
To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D020 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 27 mW and from which recovery is 800 ns.
The ADC10D020's speed, resolution and single supply operation makes it well suited for a variety of applications, including high speed portable applications.
Operating over the industrial (−40° ≤ TA≤ +85°C) temperature range, the ADC10D020 is available in a 48-pin TQFP package. An evaluation board is available to ease the design effort.
The ADC10D020 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 30 MSPS while consuming a typical 150 mW from a single 3.0V supply. No missing codes is ensured over the full operating temperature range. The unique two stage architecture achieves 9.5 Effective Bits over the entire Nyquist band at 20 MHz sample rate. An output formatting choice of offset binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error.
To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D020 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 27 mW and from which recovery is 800 ns.
The ADC10D020's speed, resolution and single supply operation makes it well suited for a variety of applications, including high speed portable applications.
Operating over the industrial (−40° ≤ TA≤ +85°C) temperature range, the ADC10D020 is available in a 48-pin TQFP package. An evaluation board is available to ease the design effort. |
ADC10D040Dual-Channel, 10-Bit, 40-MSPS Analog-to-Digital Converter (ADC) | Analog to Digital Converters (ADC) | 1 | Active | The ADC10D040 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 45 MSPS while consuming a typical 267 mW from a single 3.3V supply. No missing codes is specified over the full operating temperature range. The unique two stage architecture achieves 9.4 Effective Bits over the entire Nyquist band at 40 MHz sample rate. An output formatting choice of offset binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error.
To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D040 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 30 mW and from which recovery is 800 ns.
The ADC10D040's speed, resolution and single supply operation make it well suited for a variety of applications, including high speed portable applications.
Operating over the industrial (−40° ≤ TA≤ +85°C) temperature range, the ADC10D040 is available in a 48-pin TQFP. An evaluation board is available to ease the design effort.
The ADC10D040 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 45 MSPS while consuming a typical 267 mW from a single 3.3V supply. No missing codes is specified over the full operating temperature range. The unique two stage architecture achieves 9.4 Effective Bits over the entire Nyquist band at 40 MHz sample rate. An output formatting choice of offset binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error.
To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D040 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 30 mW and from which recovery is 800 ns.
The ADC10D040's speed, resolution and single supply operation make it well suited for a variety of applications, including high speed portable applications.
Operating over the industrial (−40° ≤ TA≤ +85°C) temperature range, the ADC10D040 is available in a 48-pin TQFP. An evaluation board is available to ease the design effort. |
ADC10D100010-Bit, Dual 1.0-GSPS or Single 2.0-GSPS Analog-to-Digital Converter (ADC) | Integrated Circuits (ICs) | 1 | Active | The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.
The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes. |
ADC10D150010-Bit, Dual 1.5-GSPS or Single 3.0-GSPS Analog-to-Digital Converter (ADC) | Integrated Circuits (ICs) | 2 | Active | The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.
The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.
The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes. |
ADC10DL065Dual-Channel, 10-Bit, 65-MSPS Analog-to-Digital Converter (ADC) | Analog to Digital Converters (ADC) | 1 | Active | The ADC10DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC10DL065 achieves 9.8 effective bits at nyquist and consumes just 370 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.
The differential inputs provide a full scale differential input swing equal to 2 times VREFwith the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 10-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.
To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.
The ADC10DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC10DL065 achieves 9.8 effective bits at nyquist and consumes just 370 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.
The differential inputs provide a full scale differential input swing equal to 2 times VREFwith the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 10-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.
To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process. |
