| FIFOs Memory | 8 | Active | |
| Logic | 3 | Active | |
74ACT74Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset | Integrated Circuits (ICs) | 18 | Active | The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.
A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.
A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. |
| Integrated Circuits (ICs) | 6 | Obsolete | |
| Integrated Circuits (ICs) | 7 | Active | The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to
67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCCand GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.
The SN74ACT7803 is characterized for operation from 0°C to 70°C.
The SN74ACT7803 is a 512-word × 18-bit FIFO suited for buffering asynchronous datapaths up to
67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCCand GND pins, along with Texas Instruments patented output edge control (OECTM) circuit, dampen simultaneous switching noise.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels. The OR flag indicates that valid data is present on the output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET\ must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.
The SN74ACT7803 is characterized for operation from 0°C to 70°C. |
| Integrated Circuits (ICs) | 5 | Active | |
| Logic | 5 | Obsolete | |
| FIFOs Memory | 6 | Active | |
| FIFOs Memory | 7 | Obsolete | |
| FIFOs Memory | 6 | Obsolete | |
