Analog Devices

The ADGS1612 contains four independent single-pole/single-throw (SPST) switches. A serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features, including cyclic redundancy check (CRC) error detection, invalid read/write address detection, and serial clock (SCLK) count error detection.It is possible to daisy-chain multiple ADGS1612 devices together. Daisy-chaining enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS1612 can also operate in burst mode to decrease the time between SPI commands.Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.The ultralow on resistance (RON) of these switches make them ideal solutions for data acquisition and gain switching applications where low RONand low distortion are critical. The RONprofile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. The ADGS1612 exhibits break-before-make switching action for use in multiplexer applications. Note that throughout this data sheet, the multifunction pin,RESET/VL, is referred to either by the entire pin name or by a single function of the pin, for example, VL, when only that function is relevant.Product HighlightThe SPI interface removes the need for parallel conversion and logic traces and reduces general-purpose input/output (GPIO) channel count.Daisy-chain mode removes additional logic traces when multiple devices are used.CRC, invalid read/write address, and SCLK count error detection ensure a robust digital interface.CRC error detection capabilities allow the use of the ADGS1612 in safety critical systems.Guaranteed break-before-make switching allows the use of the ADGS1612 in multiplexer configurations with external wiring.Minimum distortion.ApplicationsCommunication systemsMedical systemsAudio and video signal routingAutomatic test equipmentData acquisition systemsBattery-powered systemsSample-and-hold systemsRelay replacements

The ADGS2414D contains eight independent, low on-resistance, single-pole/single-throw (SPST) switches in a 4 mm x 5 mm, 30 pin LGA package.The ADGS2414D enables higher channel density in systems where printed circuit board space is constrained or existing system form factors restrict expansion.When using SPI daisy-chain mode, the unique route through pins, provide considerable space savings when multiple ADGS2414D instances are combined to design very high channel count systems, such as large switching matrices and fanout applications. The integrated supply decoupling capacitors and SDO pullup resistor further increase the space savings and reduce printed circuit board complexity.The low on-resistance (0.56 Ω typical) of each switch channel allows for higher current density in systems where heat dissipation is an issue, and the on-resistance profile of the switch channels is exceptionally flat over the full-analog input range, which ensures good linearity and low distortion when switching precision analog signals.Each switch has an input signal range from VSSto VDD– 2 V. When on, each switch conducts equally well in both directions, and in the off condition, signal levels up to the supplies are blocked. The SPI has robust error detection features, such as cyclic redundancy check (CRC) error detection, invalid read and write address detection, and SCLK count error detection.ApplicationsAutomatic test equipmentInstrumentationData acquisitionRelay replacementAvionicsAudio and video switchingCommunication systems

The ADGS5414 contains eight independent single-pole/single-throw (SPST) switches. An SPI interface controls the switches and has robust error detection features, including cyclic redundancy check (CRC) error detection, invalid read/write address error detection, and SCLK count error detection.It is possible to daisy-chain multiple ADGS5414 devices together. This enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS5414 can also operate in burst mode to decrease the time between SPI commands.Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.The on-resistance profile is flat over the full analog input range, ensuring ideal linearity and low distortion when switching audio signals. The ADGS5414 exhibits break-before-make switching action, allowing the use of the device in multiplexer applications with external wiring.Product HighlightsThe SPI interface removes the need for parallel conversion, logic traces, and reduces the general-purpose input/output (GPIO) channel count.Daisy-chain mode removes the need for additional logic traces when using multiple devices.CRC error detection, invalid read/write address error detenction, and SCLK count error detection ensures a robust digital interface.CRC and error detection capabilities allow the use of the ADGS5414 in safety critical systems.Break-before-make switching allows external wiring of the switches to deliver multiplexer configurations.The trench isolation analog switch section guards against latch-up. A dielectric trench separates the positive and negative channel transistors, preventing latch-up even under severe overvoltage conditions.ApplicationsRelay replacementAutomatic test equipmentData acquisitionInstrumentationAvionicsAudio and video switchingCommunication systems

The ADH987S 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with fast rise / fall times. The low skew outputs of the ADH987S, combined with its fast rise / fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs / DACs or SERDES devices. The noise floor is particularly important in these applications, when the clock network bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the ADH987S have a noise floor of -155 dBc/Hz.The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.ApplicationsRF/µWClock DistributionClock FanoutLO Distribution

The ADIN1100 is a low power, single port, 10BASE-T1L transceiver designed for industrial Ethernet applications and is compliant with the IEEE®802.3cg-2019™Ethernet standard for long reach 10 Mbps single pair Ethernet (SPE). The ADIN1100 integrates an Ethernet PHY core with all the associated analog circuitry, input and output clock buffering, the management interface control register and subsystem registers, as well as the MAC interface and control logic to manage the reset, clock control, and pin configuration.The ADIN1100 supports cable reach of up to 1700 meters with autonegotiation enabled and has ultra low power consumption of 39 mW.The PHY core supports the 1.0 V p-p operating mode and the 2.4 V p-p operating mode defined in the IEEE 802.3cg standard and can operate from a single power supply rail of 1.8 V or 3.3 V, with the lower voltage option supporting the 1.0 V p-p transmit voltage level.The ADIN1100 has an integrated voltage supply monitoring circuit and power-on reset (POR) circuitry to improve system level robustness.The MDIO interface is a 2-wire serial interface for communication between a host processor or MAC and the ADIN1100, thereby allowing access to control and status information in the PHY core management registers. This interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.APPLICATIONSProcess ControlFactory AutomationBuilding AutomationField instruments and switches

The ADIN1110 is an ultra low power, single port, 10BASE-T1L transceiver design for industrial Ethernet applications and is compliant with the IEEE®802.3cg-2019™Ethernet standard for long reach, 10 Mbps single pair Ethernet (SPE). Featuring an integrated media access control (MAC) interface, the ADIN1110 enables direct connectivity with a variety of host controllers via a 4-wire serial peripheral interface (SPI). This SPI enables the use of lower power processors without an integrated MAC, which provides for the lowest overall system level power consumption. The SPI can be configured to use the Open Alliance SPI protocol or a generic SPI protocol.The programmable transmit levels, external termination resistors, and independent receive and transmit pins make the ADIN1110 suited to intrinsic safety applications.The ADIN1110 has an integrated voltage supply monitoring and power-on reset (POR) circuitry to improve system level robustness.The ADIN1110 is available in a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP).APPLICATIONSField instrumentsBuilding automation and fire safetyFactory automationEdge sensors and actuatorsCondition monitoring and machine connectivity

The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps Ethernet transceiver with low latency specifications designed for industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and media access control (MAC) interface and control logic to manage the reset, clock control and pin configuration.The ADIN1200 is available in a 5 mm × 5 mm, 32-lead lead frame chip scale package (LFCSP) and can operate with a single 3.3 V supply, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1200 allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value and the power is considered good. Brownout protection is provided by monitoring the supplies to detect if one or more of them drops below a minimum falling threshold and holding the device in hardware reset until the power supplies return and satisfy the power-on-reset (POR) circuit.The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC and the ADIN1200, allowing access to control and status information in the PHY core management registers. The interface is compatible with both IEEE®802.3™Standard Clause 22 and Clause 45 management frame structures.The ADIN1200 can support cable lengths up to 180 meters.Note that throughout this data sheet, multifunction pins, such as XTAL_I/CLK_IN/REF_CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL_I, when only that function is relevant.ApplicationsIndustrial automationProcess controlFactory automationRobotics and motion ControlBuilding automationTest and MeasurementIndustrial internet of things (IoT)

The ADIN1300 is a low power, single port, Gigabit Ethernet transceiver with low latency and power consumption specifications primarily designed for industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and MAC interface and control logic to manage the reset and clock control and pin configuration.The ADIN1300 is available in a 6 mm × 6 mm, 40-lead lead frame chip scale package (LFCSP). The device operates with a minimum of 2 power supplies, 0.9 V and 3.3 V, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1300, allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1300 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value. Brown-out protection is provided by monitoring the supplies to detect if one or more supply drops below a minimum falling threshold (see Table 19 on the datasheet), and holding the device in hardware reset until the power supplies return and satisfy the power-on reset (POR) circuit.The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC (also known as management station (STA)) and the ADIN1300, allowing access to control and status information in the PHY core management registers. The interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.The ADIN1300 can support cable lengths up to 150 meters at Gigabit speeds and 180 meters when operating at 100 Mbps or 10 Mbps.ApplicationsIndustrial automationProcess controlFactory automationRobotics/motion controlTime sensitive networking (TSN)Building automationTest and measurementIndustrial internet of things (IoT)