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16-TSSOP
Integrated Circuits (ICs)

CD4521BPW

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Texas Instruments

FREQUENCY DIVIDER -55°C TO 125°C 16-PIN TSSOP TUBE

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16-TSSOP
Integrated Circuits (ICs)

CD4521BPW

Active
Texas Instruments

FREQUENCY DIVIDER -55°C TO 125°C 16-PIN TSSOP TUBE

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4521BPW
Count Rate13 MHz
Logic TypeDivide-by-2
Mounting TypeSurface Mount
Number of Bits per Element24
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
ResetAsynchronous
Supplier Device Package16-TSSOP
Trigger TypeNegative Edge
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.61
10$ 0.52
90$ 0.39
270$ 0.36
540$ 0.31
1080$ 0.24
2520$ 0.22
5040$ 0.20
Texas InstrumentsTUBE 1$ 0.44
100$ 0.30
250$ 0.23
1000$ 0.15

Description

General part information

CD4521B Series

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.