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16-DIP SOT38-1
Integrated Circuits (ICs)

CD4521BEG4

Unknown
Texas Instruments

IC DIVIDER BY 2 24-BIT 16DIP

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16-DIP SOT38-1
Integrated Circuits (ICs)

CD4521BEG4

Unknown
Texas Instruments

IC DIVIDER BY 2 24-BIT 16DIP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4521BEG4
Count Rate13 MHz
Logic TypeDivide-by-2
Mounting TypeThrough Hole
Number of Bits per Element24
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
ResetAsynchronous
Supplier Device Package16-PDIP
Trigger TypeNegative Edge
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1650$ 0.25

Description

General part information

CD4521B Series

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

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Technical documentation and resources

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