Zenode.ai Logo
Beta
Log InSign Up
SOIC (D)
Integrated Circuits (ICs)

CD4521BM

Obsolete
Texas Instruments

CMOS 24-STAGE FREQUENCY DIVIDER

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)Logic Guide (Rev. AB)+5
SOIC (D)
Integrated Circuits (ICs)

CD4521BM

Obsolete
Texas Instruments

CMOS 24-STAGE FREQUENCY DIVIDER

Deep-Dive with AI

DocumentsUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)Logic Guide (Rev. AB)+5

Technical Specifications

Parameters and characteristics for this part

SpecificationCD4521BM
Count Rate13 MHz
Logic TypeDivide-by-2
Mounting TypeSurface Mount
Number of Bits per Element24
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
ResetAsynchronous
Supplier Device Package16-SOIC
Trigger TypeNegative Edge
Voltage - Supply [Max]18 V
Voltage - Supply [Min]3 V

CD4521B Series

CMOS 24-Stage Frequency Divider

PartTrigger TypeVoltage - Supply [Max]Voltage - Supply [Min]Logic TypeNumber of Bits per ElementResetCount RatePackage / CasePackage / Case [x]Package / Case [y]Supplier Device PackageMounting TypeNumber of ElementsOperating Temperature [Min]Operating Temperature [Max]Package / CasePackage / Case
SOIC (D)
Texas Instruments
CD4521BMT
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-SOIC
0.154 in
3.9 mm
16-SOIC
Surface Mount
1
-55 °C
125 °C
16-TSSOP
Texas Instruments
CD4521BPWR
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-TSSOP
0.173 in
4.4 mm
16-TSSOP
Surface Mount
1
-55 °C
125 °C
16-TSSOP
Texas Instruments
CD4521BPW
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-TSSOP
0.173 in
4.4 mm
16-TSSOP
Surface Mount
1
-55 °C
125 °C
16 SOIC
Texas Instruments
CD4521BM96G4
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-SOIC
0.154 in
3.9 mm
16-SOIC
Surface Mount
1
-55 °C
125 °C
SOIC (D)
Texas Instruments
CD4521BM
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-SOIC
0.154 in
3.9 mm
16-SOIC
Surface Mount
1
-55 °C
125 °C
SOP (NS)
Texas Instruments
CD4521BNSR
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-SOIC
16-SO
Surface Mount
1
-55 °C
125 °C
0.209 "
5.3 mm
16 SOIC
Texas Instruments
CD4521BM96
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-SOIC
0.154 in
3.9 mm
16-SOIC
Surface Mount
1
-55 °C
125 °C
16-DIP SOT38-1
Texas Instruments
CD4521BEG4
Negative Edge
18 V
3 V
Divide-by-2
24
Asynchronous
13 MHz
16-DIP
16-PDIP
Through Hole
1
-55 °C
125 °C
0.3 in
7.62 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 1.28
10$ 1.14
40$ 1.08
120$ 0.89
280$ 0.83
520$ 0.73
Texas InstrumentsTUBE 1$ 0.95
100$ 0.73
250$ 0.54
1000$ 0.38

Description

General part information

CD4521B Series

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.