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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LV10APWRG4 |
|---|---|
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Current - Quiescent (Max) [Max] | 20 µA |
| Input Logic Level - High | 1.5 V |
| Input Logic Level - Low | 0.5 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 7.9 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 3 |
| Number of Inputs | 3 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74LV10A Series
These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCCoperation. The SN74LV10A devices perform the Boolean function Y =A • B • Cin positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCCoperation. The SN74LV10A devices perform the Boolean function Y =A • B • Cin positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
Documents
Technical documentation and resources
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