Specification	CD74HCT74M96

Clock Frequency	50 MHz
Current - Output High, Low [custom]	4 mA
Current - Output High, Low [custom]	4 mA
Current - Quiescent (Iq)	4 çA
Function	Reset, Set(Preset)
Input Capacitance	10 pF
Max Propagation Delay @ V, Max CL	35 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	14-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74HCT74 Series

High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset

Part	Input Capacitance	Operating Temperature [Max]	Operating Temperature [Min]	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case [y]	Package / Case [x]	Trigger Type	Current - Quiescent (Iq)	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Elements	Output Type	Number of Bits per Element	Clock Frequency	Max Propagation Delay @ V, Max CL	Mounting Type	Function	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Package / Case [custom]	Package / Case [custom]	Package / Case	Package / Case
Texas Instruments SN74HCT74N	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-DIP	7.62 mm	0.3 "	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Through Hole	Reset Set(Preset)
Texas Instruments SN74HCT74DRE4	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-SOIC	3.9 mm	0.154 in	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Surface Mount	Reset Set(Preset)
Texas Instruments SN74HCT74DG4	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-SOIC	3.9 mm	0.154 in	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Surface Mount	Reset Set(Preset)
Texas Instruments CD74HCT74M	10 pF			D-Type	4.5 V	5.5 V	14-SOIC	3.9 mm	0.154 in	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	50 MHz	35 ns	Surface Mount	Reset Set(Preset)	125 °C	-55 °C
Texas Instruments SN74HCT74NSR	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-SOIC	5.3 mm	0.209 "	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Surface Mount	Reset Set(Preset)			14-SO
Texas Instruments SN74HCT74DRG4	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-SOIC	3.9 mm	0.154 in	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Surface Mount	Reset Set(Preset)
Texas Instruments CD74HCT74E	10 pF			D-Type	4.5 V	5.5 V	14-DIP	7.62 mm	0.3 "	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	50 MHz	35 ns	Through Hole	Reset Set(Preset)	125 °C	-55 °C
Texas Instruments SN74HCT74PW	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-TSSOP			Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Surface Mount	Reset Set(Preset)			14-TSSOP	0.173 "	4.4 mm
Texas Instruments SN74HCT74DBR	3 pF	85 °C	-40 °C	D-Type	4.5 V	5.5 V	14-SSOP			Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	46 MHz	25 ns	Surface Mount	Reset Set(Preset)			14-SSOP			5.3 mm	0.209 "
Texas Instruments CD74HCT74M96	10 pF			D-Type	4.5 V	5.5 V	14-SOIC	3.9 mm	0.154 in	Positive Edge	4 çA	4 mA	4 mA	2	Complementary	1	50 MHz	35 ns	Surface Mount	Reset Set(Preset)	125 °C	-55 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.53
		10	$ 0.46
		25	$ 0.42
		100	$ 0.34
		250	$ 0.32
		500	$ 0.27
		1000	$ 0.21
	Digi-Reel®	1	$ 0.53
		10	$ 0.46
		25	$ 0.42
		100	$ 0.34
		250	$ 0.32
		500	$ 0.27
		1000	$ 0.21
	Tape & Reel (TR)	2500	$ 0.19
		5000	$ 0.18
		12500	$ 0.16
		25000	$ 0.16
		62500	$ 0.15
Texas Instruments	LARGE T&R	1	$ 0.28
		100	$ 0.19
		250	$ 0.15
		1000	$ 0.10

Description

General part information

SN74HCT74 Series

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.