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14-PDIP
Integrated Circuits (ICs)

SN74HCT74N

Active
Texas Instruments

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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14-PDIP
Integrated Circuits (ICs)

SN74HCT74N

Active
Texas Instruments

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HCT74N
Clock Frequency46 MHz
Current - Output High, Low [custom]4 mA
Current - Output High, Low [custom]4 mA
Current - Quiescent (Iq)4 çA
FunctionReset, Set(Preset)
Input Capacitance3 pF
Max Propagation Delay @ V, Max CL25 ns
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case14-DIP
Package / Case [x]0.3 "
Package / Case [y]7.62 mm
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

SN74HCT74 Series

High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset

PartInput CapacitanceOperating Temperature [Max]Operating Temperature [Min]TypeVoltage - Supply [Min]Voltage - Supply [Max]Package / CasePackage / Case [y]Package / Case [x]Trigger TypeCurrent - Quiescent (Iq)Current - Output High, Low [custom]Current - Output High, Low [custom]Number of ElementsOutput TypeNumber of Bits per ElementClock FrequencyMax Propagation Delay @ V, Max CLMounting TypeFunctionOperating Temperature [Max]Operating Temperature [Min]Supplier Device PackagePackage / Case [custom]Package / Case [custom]Package / CasePackage / Case
14-PDIP
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-DIP
7.62 mm
0.3 "
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Through Hole
Reset
Set(Preset)
SOIC (D)
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-SOIC
3.9 mm
0.154 in
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Surface Mount
Reset
Set(Preset)
14-SOIC
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-SOIC
3.9 mm
0.154 in
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Surface Mount
Reset
Set(Preset)
SOIC (D)
Texas Instruments
10 pF
D-Type
4.5 V
5.5 V
14-SOIC
3.9 mm
0.154 in
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
50 MHz
35 ns
Surface Mount
Reset
Set(Preset)
125 °C
-55 °C
14-SO
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-SOIC
5.3 mm
0.209 "
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Surface Mount
Reset
Set(Preset)
14-SO
14-SOIC
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-SOIC
3.9 mm
0.154 in
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Surface Mount
Reset
Set(Preset)
PDIP (N)
Texas Instruments
10 pF
D-Type
4.5 V
5.5 V
14-DIP
7.62 mm
0.3 "
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
50 MHz
35 ns
Through Hole
Reset
Set(Preset)
125 °C
-55 °C
14-TSSOP
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-TSSOP
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Surface Mount
Reset
Set(Preset)
14-TSSOP
0.173 "
4.4 mm
SN74AC86D
Texas Instruments
3 pF
85 °C
-40 °C
D-Type
4.5 V
5.5 V
14-SSOP
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
46 MHz
25 ns
Surface Mount
Reset
Set(Preset)
14-SSOP
5.3 mm
0.209 "
SOIC (D)
Texas Instruments
10 pF
D-Type
4.5 V
5.5 V
14-SOIC
3.9 mm
0.154 in
Positive Edge
4 çA
4 mA
4 mA
2
Complementary
1
50 MHz
35 ns
Surface Mount
Reset
Set(Preset)
125 °C
-55 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.64
10$ 0.57
25$ 0.53
100$ 0.43
250$ 0.40
500$ 0.34
1000$ 0.27
2500$ 0.25
5000$ 0.23
NewarkEach 1$ 0.90
10$ 0.83
100$ 0.75
500$ 0.70
1000$ 0.66
2500$ 0.62
10000$ 0.61
Texas InstrumentsTUBE 1$ 0.55
100$ 0.37
250$ 0.29
1000$ 0.19

Description

General part information

SN74HCT74 Series

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.