
CD74HCT74E
ActiveHIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED D FLIP-FLOPS WITH SET AND RESET
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CD74HCT74E
ActiveHIGH SPEED CMOS LOGIC DUAL POSITIVE-EDGE-TRIGGERED D FLIP-FLOPS WITH SET AND RESET
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HCT74E |
|---|---|
| Clock Frequency | 50 MHz |
| Current - Output High, Low [custom] | 4 mA |
| Current - Output High, Low [custom] | 4 mA |
| Current - Quiescent (Iq) | 4 çA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 10 pF |
| Max Propagation Delay @ V, Max CL | 35 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Complementary |
| Package / Case | 14-DIP |
| Package / Case [x] | 0.3 " |
| Package / Case [y] | 7.62 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.66 | |
| 10 | $ 0.58 | |||
| 25 | $ 0.54 | |||
| 100 | $ 0.44 | |||
| 250 | $ 0.41 | |||
| 500 | $ 0.35 | |||
| 1000 | $ 0.28 | |||
| 2500 | $ 0.25 | |||
| 5000 | $ 0.24 | |||
| Newark | Each | 1 | $ 0.89 | |
| 10 | $ 0.82 | |||
| 100 | $ 0.75 | |||
| 500 | $ 0.71 | |||
| 1000 | $ 0.67 | |||
| 2500 | $ 0.64 | |||
| 5000 | $ 0.63 | |||
| Texas Instruments | TUBE | 1 | $ 0.55 | |
| 100 | $ 0.37 | |||
| 250 | $ 0.29 | |||
| 1000 | $ 0.19 | |||
Description
General part information
SN74HCT74 Series
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
Documents
Technical documentation and resources