Zenode.ai Logo
Beta
Log InSign Up
16-DIP SOT38-1
Integrated Circuits (ICs)

SN74F112N

Active
Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsPower-Up Behavior of Clocked Devices (Rev. B)Logic Guide (Rev. AB)+8
16-DIP SOT38-1
Integrated Circuits (ICs)

SN74F112N

Active
Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET

Deep-Dive with AI

DocumentsPower-Up Behavior of Clocked Devices (Rev. B)Logic Guide (Rev. AB)+8

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74F112N
Clock Frequency130 MHz
Current - Output High, Low [custom]1 mA
Current - Output High, Low [custom]20 mA
Current - Quiescent (Iq)19 mA
FunctionReset, Set(Preset)
Max Propagation Delay @ V, Max CL6.5 ns
Mounting TypeThrough Hole
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeComplementary
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
Supplier Device Package16-PDIP
Trigger TypeNegative Edge
TypeJK Type
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

SN74F112 Series

Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset

PartCurrent - Output High, Low [custom]Current - Output High, Low [custom]Mounting TypePackage / CasePackage / CasePackage / CaseClock FrequencyVoltage - Supply [Min]Voltage - Supply [Max]Max Propagation Delay @ V, Max CLNumber of ElementsTypeOperating Temperature [Max]Operating Temperature [Min]Trigger TypeOutput TypeNumber of Bits per ElementCurrent - Quiescent (Iq)Supplier Device PackageFunctionPackage / Case [x]Package / Case [y]
16-DIP SOT38-1
Texas Instruments
SN74F112N
1 mA
20 mA
Through Hole
0.3 in
16-DIP
7.62 mm
130 MHz
4.5 V
5.5 V
6.5 ns
2
JK Type
70 °C
0 °C
Negative Edge
Complementary
1
19 mA
16-PDIP
Reset
Set(Preset)
16-DIP SOT38-1
Texas Instruments
SN74F112NG4
1 mA
20 mA
Through Hole
0.3 in
16-DIP
7.62 mm
130 MHz
4.5 V
5.5 V
6.5 ns
2
JK Type
70 °C
0 °C
Negative Edge
Complementary
1
19 mA
16-PDIP
Reset
Set(Preset)
16 SOIC
Texas Instruments
SN74F112D
1 mA
20 mA
Surface Mount
16-SOIC
130 MHz
4.5 V
5.5 V
6.5 ns
2
JK Type
70 °C
0 °C
Negative Edge
Complementary
1
19 mA
16-SOIC
Reset
Set(Preset)
0.154 in
3.9 mm
16 SO
Texas Instruments
SN74F112NSR
1 mA
20 mA
Surface Mount
0.209 "
16-SOIC
5.3 mm
130 MHz
4.5 V
5.5 V
6.5 ns
2
JK Type
70 °C
0 °C
Negative Edge
Complementary
1
19 mA
16-SO
Reset
Set(Preset)

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.85
10$ 0.76
25$ 0.72
100$ 0.59
250$ 0.55
500$ 0.49
1000$ 0.39
2500$ 0.36
5000$ 0.34
Texas InstrumentsTUBE 1$ 0.72
100$ 0.56
250$ 0.41
1000$ 0.29

Description

General part information

SN74F112 Series

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

The SN74F112 is characterized for operation from 0°C to 70°C.

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.